PHN70308 Datasheet, PDF (5/10 Pages) NXP Semiconductors – N-channel enhancement mode TrenchMOS transistor array

Philips Semiconductors
N-channel enhancement mode
TrenchMOS transistor array
Product specification
PHN70308
Drain current, ID (A)
1.0E-01
VDS = 5 V
1.0E-02
1.0E-03
minimum
1.0E-04
typical
1.0E-05
1.0E-06
0
0.5
1
1.5
2
2.5
3
Gate-source voltage, VGS (V)
Fig.5. Sub-threshold drain current.
I_D = f(V_GS); conditions: T_j = 25 ˚C
100 ^{Peak Pulsed Drain Current, IDM (A)}
RDS(on) = VDS/ ID
10
tp = 10 us
100 us
1 ms
1
D.C.
10 ms
100 ms
0.1
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Fig.6. Safe operating area (spindle FET) T_sp = 25˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
100 ^{Peak Pulsed Drain Current, IDM (A)}
RDS(on) = VDS/ ID
10
D.C.
1
tp = 100 us
1 ms
10 ms
100 ms
0.1
0.1
1
10
100
Drain-Source Voltage, VDS (V)
Fig.7. Safe operating area (isolation FET) T_sp = 25˚C
I_D & I_DM = f(V_DS); I_DM single pulse; parameter t_p
Transient thermal impedance, Zth j-a (K/W)
100
D = 0.5
0.2
10
0.1
0.05
1 0.02
0.1 _{single pulse}
P
D
D = tp/T
tp
0.01
1E-06
1E-05
1E-04
1E-03
1E-02
Pulse width, tp (s)
T
1E-01 1E+00 1E+01
Fig.8. Transient thermal impedance (spindle FET).
Z_{th j-sp} = f(t); parameter D = t_p/T
Transient thermal impedance, Zth j-a (K/W)
100
D = 0.5
10
0.2
0.1
1
0.05
0.02
single pulse
0.1
P
D
D = tp/T
tp
0.01
1E-06
1E-05
1E-04
1E-03 1E-02
Pulse width, tp (s)
T
1E-01 1E+00 1E+01
Fig.9. Transient thermal impedance (isolation FET).
Z_{th j-sp} = f(t); parameter D = t_p/T
Drain Current, ID (A)
8
VGS = 10 V
7
6
4.5 V
Tj = 25 C
5
3.6 V
4
3.4 V
3
3.2 V
2
3V
1
2.8 V
2.6 V
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Drain-Source Voltage, VDS (V)
Fig.10. Typical output characteristics (spindle FET)
T_j = 25 ˚C; I_D = f(V_DS); parameter V_GS
May 1999
5
Rev 1.000