SAA4992H Datasheet, PDF (6/36 Pages) NXP Semiconductors – Field and line rate converter with noise reduction

Philips Semiconductors
Field and line rate converter with noise
reduction
Product specification
SAA4992H
6 PINNING
SYMBOL PIN
V_SSE
1
YC0
2
YC1
3
YC2
4
YC3
5
YC4
6
YC5
7
YC6
8
YC7
9
UVC0
10
UVC1
11
UVC2
12
UVC3
13
REC
14
V_SSE
15
V_DDE
16
V_SSI
17
V_DDI
18
JUMP0
19
JUMP1
20
V_DDE
21
V_DDI
22
V_SSI
23
RAMTST1 24
SNRST
25
SNDA
26
SNCL
27
V_SSE
28
RAMTST2 29
TEST
30
TRST
31
TMS
32
TDI
33
TDO
34
TYPE
DESCRIPTION⁽¹⁾⁽²⁾
ground ground of output pads
input bus C luminance input from field memory 2 bit 0 (LSB)
input bus C luminance input from field memory 2 bit 1
input bus C luminance input from field memory 2 bit 2
input bus C luminance input from field memory 2 bit 3
input bus C luminance input from field memory 2 bit 4
input bus C luminance input from field memory 2 bit 5
input bus C luminance input from field memory 2 bit 6
input bus C luminance input from field memory 2 bit 7 (MSB)
input bus C chrominance input from field memory 2 bit 0 (LSB)
input bus C chrominance input from field memory 2 bit 1
input bus C chrominance input from field memory 2 bit 2
input bus C chrominance input from field memory 2 bit 3 (MSB)
output read enable output for bus C
ground ground of output pads
supply supply voltage of output pads
ground core ground
supply core supply voltage
input
input
configuration pin 0; will be stored in register 0B3 e.g. to indicate presence of 3rd field
memory; should be connected to ground or to V_DDI via pull-up resistor; note 3
configuration pin 1; will be stored in register 0B5 e.g. to indicate presence of 16-bit
1st field memory for full 4 : 2 : 2; should be connected to ground or to V_DDI via
pull-up resistor; note 3
supply supply voltage of output pads
supply core supply voltage
ground core ground
input test pin 1 for internal RAM testing; connect to ground for normal operation
input SNERT bus reset
I/O SNERT bus data
input SNERT bus clock
ground ground of output pads
input test pin 2 for internal RAM testing; connect to ground for normal operation
input test mode input; if not used it has to be connected to ground
input boundary scan test: reset input signal; if not used it has to be connected to ground via
pull-down resistor; note 3
input boundary scan test: test mode select; if not used it has to be connected to V_DDI via
pull-up resistor; note 3
input boundary scan test: data input signal; if not used it has to be connected to V_DDI via
pull-up resistor; note 3
output boundary scan test: data output signal
2000 Feb 04
6