SAA4992H Datasheet, PDF (29/36 Pages) NXP Semiconductors – Field and line rate converter with noise reduction

Philips Semiconductors
Field and line rate converter with noise
reduction
Product specification
SAA4992H
SYMBOL
PARAMETER
CONDITIONS MIN.
Input CLK32; see Fig.5
t_r
rise time
−
t_f
fall time
−
δ
duty factor
40
T_cy
cycle time
30
SNERT interface; see Fig.7
t_SNRSTH
SNRST pulse HIGH time
500
t_d(SNRST-SNCL) delay SNRST pulse to SNCL LOW time
200
T_cy(SNCL)
SNCL cycle time
0.5
t_su(i)(SNCL)
input set-up time to SNCL
53
t_h(i)(SNCL)
input hold time to SNCL
10
t_h(o)
output hold time
30
t_d(o)
output delay time
−
t_o(en)
output enable time
210
BST interface; see Fig.6
T_cy(BST)
BST cycle time
−
t_su(i)(BST)
input set-up time
3
t_h(i)(BST)
input hold time
6
t_h(o)(BST)
output hold time
4
t_d(o)(BST)
output delay time
−
Notes
1. Timing characteristics are measured with C_L = 15 pF; I_OL = 2 mA; R_L = 2 kΩ.
2. All inputs except SNERT, CLK32 and BST.
TYP.
−
−
−
−
−
−
−
−
−
−
−
−
1
−
−
−
−
MAX.
4
4
60
39
−
−
1
−
−
−
330
−
−
−
−
−
30
UNIT
ns
ns
%
ns
ns
ns
µs
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
2000 Feb 04
29