SAA4992H Datasheet, PDF(27/36 Page) NXP Semiconductors – Field and line rate converter with noise reduction

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SAA4992H Datasheet, PDF (27/36 Pages) NXP Semiconductors – Field and line rate converter with noise reduction

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NAME

SNERT

ADDRESS

HEX

READ/

WRITE(1)

DESCRIPTION(2)

PanZoomVec2-Y

0B5

StatusJump1

PanZoomVec2-Y

PanZoomVec3-X

0B6

PanZoomVec3-Y

0B7

PanZoomVec4-X

0B8

PanZoomVec4-Y

0B9

PanZoomVec5-X

0BA

PanZoomVec5-Y

0BB

PanZoomVec6-X

0BC

PanZoomVec6-Y

0BD

PanZoomVec7-X

0BE

PanZoomVec7-Y

0BF

PanZoomVec8-X

0AE

PanZoomVec8-Y

0AF

EggSliceRgtMSB

0C0

EggSliceRgtLSB

0C1

EggSliceMixMSB

0C2

EggSliceMixLSB

0C3

read

read; F

read out of conï¬guration pin JUMP1

X X X X X X X pan-zoom vector 2 (7-bit Y value)

X X X X X X X X pan-zoom vector 2 (8-bit X value)

X X X X X X X pan-zoom vector 3 (7-bit Y value)

X X X X X X X X pan-zoom vector 4 (8-bit X value)

X X X X X X X pan-zoom vector 4 (7-bit Y value)

X X X X X X X X pan-zoom vector 5 (8-bit X value)

X X X X X X X pan-zoom vector 5 (7-bit Y value)

X X X X X X X X pan-zoom vector 6 (8-bit X value)

X X X X X X X pan-zoom vector 6 (7-bit Y value)

X X X X X X X X pan-zoom vector 7 (8-bit X value)

X X X X X X X pan-zoom vector 7 (7-bit Y value)

X X X X X X X X pan-zoom vector 8 (8-bit X value)

X X X X X X X pan-zoom vector 8 (7-bit Y value)

X X X X X X X X result of right pixels egg-slice detector (15 to 8)

X X X X X X X X result of right pixels egg-slice detector (7 to 0)

X X X X X X X X result of mixed pixels egg-slice detector (15 to 8)

X X X X X X X X result of mixed pixels egg-slice detector (7 to 0)

Notes

1. S means semi static, used at initialization or mode changes; F means field frequent, in general updated in each display field.

2. Selectable items are marked bold.

3. Almost all of the R(ead) and W(rite) registers of SAA4992H are double buffered. The Write registers are latched by a signal called New_field.

New_field gets set, when RE_f rises after RSTR (New_field is effectively at the start of active video). The Read registers are latched by a signal

called Reg_upd. Reg_upd gets set, when half the number of active pixels of the fourth line of vertical blanking have entered the SAA4992H

(Reg_upd will effectively be active 3 and a halve lines after the RE_a, RE_c and RE_e have ended). The only exceptional registers, which are not

double buffered, are:

a) Write register 025: power_on_reset

b) Write register 02F, bit 1: CndSet

c) Read register 0B0 to 0BF, 0AE and 0AF: pan_zoom_vectors, including FalconIdent (= 0), jump0 and jump1.

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