SAA4992H Datasheet, PDF (12/36 Pages) NXP Semiconductors – Field and line rate converter with noise reduction

Philips Semiconductors
Field and line rate converter with noise
reduction
Product specification
SAA4992H
7 FUNCTIONAL DESCRIPTION
The FAL (fal_top) module builds the functional top level of
the SAA4992H. It connects the luminance data path (KER,
kernel), the chrominance data path (COL, colour) and the
luminance (de)compression (YDP, Y-DPCM) with
SAA4992H inputs and outputs as well as controlling logic
(LSE, line sequencer; SNE, SNERT interface). Outside of
fal_top there are only the pad cells, boundary scan test
cells, the boundary scan test controller, the clock tree, the
test enable tree and the input port registers.
Figure 4 shows a simplified block diagram of fal_top. It
displays the flow of pixel data (solid lines) and controls
(broken lines) between the modules inside.
Basic functionality of the modules in fal_top is as follows:
• KER (kernel): Y (luminance) data path
• COL (colour): UV (chrominance) data path
• YDP (Y-DPCM): compression (and decompression) of
luminance output (and input) data by Differential Pulse
Code Modulation (DPCM)
• LSE (line sequencer): generate line frequent control
signals
• SNE: Synchronous No parity Eight bit Reception and
Transmission (SNERT) interface to a microcontroller.
The SNERT interface operates in a slave receive and
transmit mode for communication with a microprocessor,
which resides on peripheral circuits (e.g. SAA4978H)
together with a SNERT master. The SNERT interface
transforms serial data from the microprocessor (via the
SNERT bus) into parallel data to be written into the
SAA4992Hs write registers and parallel data from
SAA4992Hs read registers into serial data to be sent to the
microprocessor. The SNERT bus consists of 3 signals:
1. SNCL: used as serial clock signal, generated by the
master
2. SNDA: used as bidirectional data line
3. SNRST: used as a reset signal, generated by the
microprocessor to indicate the start of a transmission.
The processing of a video field begins on the rising edge
of the RE_F input signal. As indicated in Fig.4, the
SAA4992H expects its inputs and generates its outputs at
the following clock cycles after RE_F (see Table 1).
Table 1 Clock cycle references
SIGNAL
RE_F
RE_C and
RE_E
YC, YE, UVC
and UVE
RE_A
YA and UVA
YF, YG, UVF
and UVG
WE_B and
WE_D
YB, YD, UVB
and UVD
LATENCY
0
63 cycles + REceShift
63 cycles
94 cycles + REaShift
94 cycles
148 cycles + 3 input lines
160 cycles + 4 input lines + WEbdShift
160 cycles + 4 input lines
There is an algorithmic delay of 3 lines between input and
output data. Therefore, the main data output on the
F and G bus begins while the fourth input line is read.
Writing to the B and D bus starts one input line later.
The read and write enable signals RE_A, WE_B, RE_C,
WE_D and RE_E can be shifted by control registers
REaShift, WEbdShift and REceShift, which are
implemented in the line sequencer.
The fal_top module itself reads the following control
register bits(addresses):
• NrofFMs (017)
• MatrixOn (026)
• MemComp and MemDecom (026).
NrofFMs and MatrixOn are used to enable the D and G
output bus, respectively. MemComp and MemDecom are
connected to YDP to control luminance data compression
and decompression. These control register signals are not
displayed in Fig.4. Further information on the control
registers is given in Chapter 8.
2000 Feb 04
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