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| PSMN020-100YS_15 Datasheet, PDF (6/14 Pages) NXP Semiconductors – N-channel 100V 20.5mΩ standard level MOSFET in LFPAK | |||
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NXP Semiconductors
PSMN020-100YS
N-channel 100V 20.5m⦠standard level MOSFET in LFPAK
Symbol
Parameter
Conditions
Dynamic characteristics
QG(tot)
total gate charge
ID = 30 A; VDS = 50 V; VGS = 10 V;
Fig. 15; Fig. 16
ID = 0 A; VDS = 0 V; VGS = 10 V
QGS
gate-source charge
ID = 30 A; VDS = 50 V; VGS = 10 V;
Fig. 15; Fig. 16
QGS(th)
pre-threshold gate-
source charge
ID = 30 A; VDS = 50 V; VGS = 10 V;
Fig. 15
QGS(th-pl)
post-threshold gate-
source charge
QGD
gate-drain charge
ID = 30 A; VDS = 50 V; VGS = 10 V;
Fig. 15; Fig. 16
VGS(pl)
gate-source plateau
voltage
VDS = 50 V; Fig. 15; Fig. 16
Ciss
input capacitance
VDS = 50 V; VGS = 0 V; f = 1 MHz;
Coss
output capacitance
Tj = 25 °C; Fig. 17
Crss
reverse transfer
capacitance
td(on)
tr
turn-on delay time
rise time
VDS = 50 V; RL = 1.7 Ω; VGS = 10 V;
RG(ext) = 4.7 Ω; Tj = 25 °C
td(off)
turn-off delay time
tf
fall time
Source-drain diode
VSD
source-drain voltage IS = 15 A; VGS = 0 V; Tj = 25 °C; Fig. 18
trr
reverse recovery time IS = 10 A; dIS/dt = 100 A/µs; VGS = 0 V;
Qr
recovered charge
VDS = 50 V
Min Typ Max Unit
-
41
57.4 nC
-
34
47.6 nC
-
10.2 14.3 nC
-
6.9 -
nC
-
3.4 -
nC
-
11.8 16.5 nC
-
4.4 -
V
-
2210 2980 pF
-
167 226 pF
-
103 144 pF
-
17.4 26.1 ns
-
18.1 27.2 ns
-
37.8 56.7 ns
-
15
22.5 ns
-
0.8 1.2 V
-
52
68
ns
-
112 146 nC
PSMN020-100YS
Product data sheet
All information provided in this document is subject to legal disclaimers.
26 March 2014
© NXP Semiconductors N.V. 2014. All rights reserved
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