TDA8031 Datasheet, PDF (35/57 Pages) NXP Semiconductors – USB smart card reader (OTP or ROM)

Philips Semiconductors
USB smart card reader (OTP or ROM)
Product specification
TDA8030; TDA8031
8.4.1 LOW POWER MODES
Stop Clock Mode: The static design enables the clock
speed to be reduced down to 0 MHz (stopped). When the
oscillator is stopped, the RAM and Special Function
Registers (SFRs) retain their values. This mode allows
step-by-step utilization and permits reduced system power
consumption by lowering the clock frequency down to any
value. The power-down mode is suggested for the lowest
power consumption.
IDLE Mode: In the Idle mode, the CPU puts itself to sleep
while all of the on-chip peripherals stay active. The
instruction to invoke the Idle mode is the last instruction
executed in the normal operating mode before the Idle
mode is activated. The CPU contents, the on-chip RAM
and all of the special function registers remain intact during
this mode. The Idle mode can be terminated either by any
enabled interrupt (at which time the process is picked up
at the interrupt service routine and continued), or by a
hardware reset which starts the processor in the same
manner as a Power-on reset.
Power-down Mode: To save even more power, a
power-down mode can be invoked by software. In this
mode, the oscillator is stopped and the instruction that
invoked the power-down is the last instruction executed.
Either a hardware reset or external interrupt can be used
to exit from the power-down mode. Applying a reset
redefines all of the SFRs but does not change the on-chip
RAM. An external interrupt allows both the SFRs and the
on-chip RAM to retain their values.
The bits in the Interface Engine (IE) must be enabled with
INT0 and INT1. Within the INT0 interrupt service routine,
the microcontroller has to read out the Hardware Status
Register (HSR at 0FH) and/or the UART Status register
(USR at 0EH) by means of MOVX instructions in order to
establish the exact interrupt reason and to reset the
interrupt source.
For enabling a wake-up by INT1, the bit ENINT1 within
UCR2 must be set.
An integrated delay counter maintains INT0 and INT1
LOW long enough to allow the oscillator to restart properly.
A falling edge on pins INT0 and INT1 is enough to awaken
the whole circuit.
Once the interrupt is serviced, the next instruction to be
executed after RETI will be the one following the
instruction that put the device into power-down.
8.5 USB INTERFACE
8.5.1 END-POINTS
The TDA8030; TDA8031 has 4 logic end-points which are
listed in Table 29.
Each physical end-point, except for the control ones, can
be enabled or disabled. All enabled end-points generate
interrupts to the microcontroller via INT1 when the
end-point needs to be serviced.
The implementation of the function makes use of an SRAM
for buffering the data.
Logic end-points can be accessed by the microcontroller
interface.
Table 29 Mapping of logic to physical end-point numbers for used end-points
END-POINT NAME
Control end-point
Generic end-point (may be used as bulk
Generic end-point (may be used as interrupt)
Generic end-point
LOGIC
END-POINT
0
1
2
3
BUFFER SIZE
16
32
8
8
PHYSICAL END-POINT
OUT
IN
0
1
2
3
−
4
−
5
2003 Jul 04
35