TDA8031 Datasheet, PDF (22/57 Pages) NXP Semiconductors – USB smart card reader (OTP or ROM)

Philips Semiconductors
USB smart card reader (OTP or ROM)
Product specification
TDA8030; TDA8031
If any of the status bits FER, OVR, PE, EA, TO1 or TO3
are set, then INT0 is LOW. The bit having caused the
interrupt is reset 2 × f_int cycles after the rising edge of RD
during a read operation of the USR. If TBE/RBF is set and
if the mask bit DISTBE/RBF within UCR2 is not set, then
INT0 is also LOW. TBE/RBF is reset 2 clock cycles after
data has been written into the UTR, or 2 clock cycles after
data has been read from the URR, or when changing from
transmission mode to reception mode if the FIFO had not
been left full when going to transmission mode. If the Last
Character to Transmit (LCT) is used for transmitting the
last character, then TBE will not be set at the end of the
transmission.
8.1.5 CARDS REGISTERS
When working with a card, the following registers may be
used for programming some specific parameters:
8.1.5.1 Programmable divider register
The Programmable Divider Register (PDR) is used for
counting the cards clock cycles which form the ETU. It is
an autoreload 8-bit counter decounting from the
programmed value down to 0.
Table 17 Programmable divider register (address 02H; read and write); note 1
7
6
5
4
3
2
PD7
PD6
PD5
PD4
PD3
PD2
Note
1. All bits are cleared after reset.
8.1.5.2 UART configuration register 2
Table 18 UART configuration register 2 (address 03H; read and write); note 1
27
26
25
ENINT1
DISTBE/
−
RBF
24
23
22
−
SAN
AUTOCONV
Note
1. All bits are cleared after reset.
1
PD1
21
CKU
0
PD0
20
PSC
2003 Jul 04
22