TDA8031 Datasheet, PDF (15/57 Pages) NXP Semiconductors – USB smart card reader (OTP or ROM)

Philips Semiconductors
USB smart card reader (OTP or ROM)
Product specification
TDA8030; TDA8031
8.1.3.2 Hardware status register
The Hardware Status Register (HSR) gives the status of the chip after a hardware problem has been detected.
Table 2 Hardware Status Register (address 0FH; read only); note 1
7
6
5
4
3
2
1
0
−
−
PRTL
SUPL
−
PRL
−
PTL
Note
1. All bits are cleared after reset.
Table 3 Description of the HSR bits
BIT
7 and 6
5
4
3
2
1
0
SYMBOL
−
PRTL
SUPL
−
PRL
−
PTL
DESCRIPTION
not used
Protection 1: Bit PRTL = 1 when a default has been detected on card reader. Bit PRTL
is the OR function of the protection on pins V_CC and RST.
Supervisor Latch: Bit SUPL = 1 when the supervisor has been activated.
not used
Presence Latch: Bit PRL = 1 when a change has occurred on pin PRES.
not used
Overheating: Bit PTL = 1 if overheating has occurred.
When either bits PRTL, PRL or PTL is logic 1, then pin INT0 is LOW. The bits having caused the interrupt are cleared
when the HSR has been readout (2 × f_int cycles after the rising edge of RD).
At power-on, or after a supply voltage drop-out, SUPL is set and INT0 is LOW. INT0 will return HIGH at the end of the
internal Power-on reset pulse defined by the value of the capacitor connected to pin CDELAY. SUPL will be reset only
after a status register readout outside the Power-on reset pulse; see Fig.8.
In the event of emergency deactivation (by PRTL, SUPL, PRL and PTL), bit START will be automatically reset by
hardware.
8.1.3.3 Time-out registers
The three Time-Out Registers TOR1, TOR2 and TOR3 form a programmable 24-bit ETU counter, or two independant
counters (one 16-bit and one 8-bit).
The value to load in TOR1, TOR2 and TOR3 is the number of ETUs to count.
Table 4 Time-out register 1 (address 09H; write only); note 1
7
TOL7
6
TOL6
5
TOL5
4
TOL4
3
TOL3
Note
1. All bits are cleared after reset.
2
TOL2
1
TOL1
0
TOL0
2003 Jul 04
15