TDA8031 Datasheet, PDF (20/57 Pages) NXP Semiconductors – USB smart card reader (OTP or ROM)

Philips Semiconductors
USB smart card reader (OTP or ROM)
Product specification
TDA8030; TDA8031
8.1.4.4 FIFO control register
The FIFO Control Register (FCR) relates the parity error count and the FIFO length.
Table 13 FIFO control register (address 0CH; write only); note 1
7
6
5
4
3
−
PEC2
PEC1
PEC0
−
Note
1. All bits are cleared after reset.
2
1
0
FL2
FL1
FL0
Table 14 Description of the FCR bits
BIT
7
6 to 4
SYMBOL
−
PEC2 to
PEC0
DESCRIPTION
not used
Parity Error Count: PEC2, PEC1 and PEC0 determine the number of parity errors
before setting the bit PE within the USR and pulling INT0 LOW; 000 means that only
one parity error has occurred and bit PE is set.
3
2 to 0
−
FL2 to FL0
The value 000 indicates that if only one parity error has occurred bit PE is set; the value
111 indicates that PE will be set after 8 parity errors.
In protocol T = 0:
• If a correct character is received before the programmed error number is reached the
error counter will be reset
• If the programmed number of allowed parity errors is reached, bit PE in the USR will
be set as long as the USR has not been read
• If a transmitted character has NAKed by the card, then the TDA8030; TDA8031 will
automatically re-transmit it a number of times equal to the value programmed in PEC2,
PEC1 and PEC0. The character will be resent at 15 ETU
• In transmission mode, if bits PEC2, PEC1 and PEC0 are at logic 0, then the automatic
re-transmission is invalidated; the character manually rewritten in the UTR will start at
13.5 ETU.
In protocol T = 1:
• The error counter has no action; bit PE is set at the first incorrectly received character.
not used
FIFO Length: Bits FL2, FL1 and FL0 determine the depth of the FIFO:
• 000 = length 1
• 111 = length 8
2003 Jul 04
20