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TDA8031 Datasheet, PDF (26/57 Pages) NXP Semiconductors – USB smart card reader (OTP or ROM)
Philips Semiconductors
USB smart card reader (OTP or ROM)
Product specification
TDA8030; TDA8031
Table 24 Description of the CCR bits
BIT
7
6
5
4
3
2 to 0
SYMBOL
DESCRIPTION
−
not used
−
not used
SHL
Stop HIGH or LOW: If bit CST = 1, then the clock is stopped at LOW level if SHL = 0
and at HIGH level if SHL = 1. In these modes, the bias current in the card drivers is
reduced; the current drawn by the card (ICC) should be less than 10 mA at all VCC
voltages.
CST
Clock stop: In case of asynchronous cards, bit CST defines whether the clock to the
card is stopped or not. If bit CST is reset, then the clock is determined by bits AC0,
AC1 and AC2; see Table 25. All frequency changes are synchronous, thus ensuring
that no spike or unwanted pulse widths occurs during changes.
SC
AC2 to AC0
Synchronous Clock: In the event of synchronous cards, the clock contact is a copy of
the value written in SC. In reception mode, the data from the card is available in bit UR0
after a read operation of the URR register. In transmission mode, bit UT0 is written on
the I/O line of the card when UTR register has been written.
When switching from 1⁄nfxtal to 1⁄2fint or vice versa, only bit AC2 must be changed;
AC1 and AC0 must remain the same. When switching from 1⁄nfxtal or 1⁄2fint to CLK STOP
or vice versa, only bits CST and SHL must be changed.
When switching from 1⁄nfxtal to 1⁄2fint or vice versa, a maximum delay of 200 µs can occur
between the command and the effective frequency change on pin CLK. The fastest
switch is from 1⁄2fxtal to 1⁄2fint or vice versa, the best duty cycle is from 1⁄8fxtal to 1⁄2fint or
vice versa. The status bit CLKSW within the MSR gives the effective switch moment.
Table 25 CLK value for an asynchronous card
AC2
AC1
AC0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Note
1. If fCLK = fXTAL, the duty cycle must be ensured by the incoming clock signal on XTAL1.
CLK(1)
fxtal
1⁄2fxtal
1⁄4fxtal
1⁄8fxtal
1⁄2fint
1⁄2fint
1⁄2fint
1⁄2fint
2003 Jul 04
26