TDA8031 Datasheet, PDF (25/57 Pages) NXP Semiconductors – USB smart card reader (OTP or ROM)

Philips Semiconductors
USB smart card reader (OTP or ROM)
Product specification
TDA8030; TDA8031
Table 22 Description of the UCR1 bits
BIT
SYMBOL
DESCRIPTION
7
−
not used
6
FIP
Force Inverse Parity: If FIP = 1, then the UART will NAK a correct received character
and will transmit characters with wrong parity bit.
5
FC
Bit FC is a test bit and must be left at logic 0.
4
PROT Protocol: Bit PROT = 1 if the protocol type is asynchronous T = 1. If PROT = 0, the
protocol is T = 0.
3
T/R
Transmit/Receive: Bit T/R is set by software for transmission mode. A change from
0 to 1 will set bit TBE in the USR. T/R is automatically reset by hardware if LCT has
been used before transmitting the last character.
2
LCT
Last Character to Transmit: Bit LCT is set by software before writing the last character
to transmit into the UTR. It allows automatic change to reception mode when reset by
hardware at the end of a successful transmission (11 + ²⁸⁄₃₁ or ²⁸⁄₃₂ ETU in T = 0 and
10 + ²⁸⁄₃₁ or ²⁸⁄₃₂ ETU in T = 1). When LCT is being reset, the bit T/R is also reset and
the UART is then ready for receiving a character.
1
SS
Start Session: Bit SS is set by software before ATR for automatic convention detection
and early answer detection. It is automatically reset by hardware at 10.5 ETU after
reception of the initial character.
0
CONV Convention: Bit CONV = 1 if the convention is direct. CONV is either automatically
written to by hardware, according to the convention detected during ATR, or by software
if bit AUTOCONV is set.
8.1.5.6 Clock configuration register
The Clock Configuration Register (CCR) defines the clock to the card and the clock to the ISO UART. If bit CKU in the
Prescaler Register (UCR2) of the card is set, then the ISO UART is clocked at twice the frequency to the card, this allows
higher baud rates to be reached than foreseen in the ISO7816 norm.
Table 23 Clock configuration register (address 01H; read and write); note 1
7
6
5
4
3
2
1
0
−
−
SHL
CST
SC
AC2
AC1
AC0
Note
1. All bits are cleared after reset.
2003 Jul 04
25