80C575 Datasheet, PDF (34/40 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
Product specification
80C575/83C575/
87C575
EPROM CHARACTERISTICS
To put the 87C575 in the EPROM
programming mode, PSEN must be held high
during power up, then driven low with reset
active. The 87C575 is programmed by using
a modified Quick-Pulse Programming™
algorithm. It differs from older methods in the
value used for V_PP (programming supply
voltage) and in the width and number of the
ALE/PROG pulses.
The 87C575 contains two signature bytes
that can be read and used by an EPROM
programming system to identify the device.
The signature bytes identify the device as an
87C575 manufactured by Philips.
Table 3 shows the logic levels for reading the
signature byte, and for programming the
program memory, the encryption table, and
the security bits. The circuit configuration and
waveforms for quick-pulse programming are
shown in Figures 34 and 35. Figure 36 shows
the circuit configuration for normal program
memory verification.
Quick-Pulse Programming
The setup for microcontroller quick-pulse
programming is shown in Figure 34. Note that
the 87C575 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to
be running is that the device is executing
internal address and program data transfers.
The address of the EPROM location to be
programmed is applied to ports 1 and 2, as
shown in Figure 34. The code byte to be
programmed into that location is applied to
port 0. RST, PSEN and pins of ports 2 and 3
specified in Table 3 are held at the ‘Program
Code Data’ levels indicated in Table 3. The
ALE/PROG is pulsed low 25 times as shown
in Figure 35.
To program the encryption table, repeat the
25 pulse programming sequence for
addresses 0 through 1FH, using the ‘Pgm
Encryption Table’ levels. Do not forget that
after the encryption table is programmed,
verification cycles will produce only encrypted
data.
To program the security bits, repeat the 25
pulse programming sequence using the ‘Pgm
Security Bit’ levels. After one security bit is
programmed, further programming of the
code memory and encryption table is
disabled. However, the other security bit can
still be programmed.
Note that the EA/V_PP pin must not be allowed
to go above the maximum specified V_PP level
for any amount of time. Even a narrow glitch
above that voltage can cause permanent
damage to the device. The V_PP source
should be well regulated and free of glitches
and overshoot.
Program Verification
If security bit 2 has not been programmed,
the on-chip program memory can be read out
for program verification. The address of the
program memory locations to be read is
applied to ports 1 and 2 as shown in
Figure 36. The other pins are held at the
‘Verify Code Data’ levels indicated in Table 3.
The contents of the address location will be
emitted on port 0. External pull-ups are
required on port 0 for this operation.
If the encryption table has been programmed,
the data presented at port 0 will be the
exclusive NOR of the program byte with one
of the encryption bytes. The user will have to
know the encryption table contents in order to
correctly decode the verification data. The
encryption table itself cannot be read out.
Reading the Signature Bytes
The signature bytes are read by the same
procedure as a normal verification of
locations 030H and 031H, except that P3.6
and P3.7 need to be pulled to a logic low. The
values are:
(030H) = 15H indicates manufactured by
Philips
(B0H) = 97H indicates 87C575
Program/Verify Algorithms
Any algorithm in agreement with the
conditions listed in Table 3, and which
satisfies the timing specifications, is suitable.
Table 3. EPROM Programming Modes
MODE
Read signature
RST
0
PSEN
0
ALE/PROG
1
EA/V_PP
1
P2.7
0
P2.6
0
P3.7
0
P3.6
0
Program code data
Verify code data
0
0
0*
V_PP
1
0
1
1
0
0
1
1
0
0
1
1
Pgm encryption table
0
0
0*
V_PP
1
0
1
0
Pgm security bit 1
0
0
0*
V_PP
1
1
1
1
Pgm security bit 2
0
0
0*
V_PP
1
1
0
0
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. V_PP = 12.75V ±0.25V.
3. V_CC = 5V±10% during programming and verification.
* ALE/PROG receives 25 programming pulses while V_PP is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a
minimum of 10µs.
™Trademark phrase of Intel Corporation.
1998 May 01
34