80C575 Datasheet, PDF (28/40 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
Product specification
80C575/83C575/
87C575
AC ELECTRICAL CHARACTERISTICS
T_amb = 0°C to +70°C and –40°C to +125°C, V_CC = 5V ±10%, V_SS = 0V^{1, 2}
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
UNIT
1/t_CLCL
22
Oscillator frequency: Speed Versions
8XC575
E
6
16
MHz
OSCF
Oscillator fail detect frequency
0.6
5.5
MHz
TR
Comparator response time
10
µs
t_LHLL
22
t_AVLL
22
t_LLAX
22
t_LLIV
22
t_LLPL
22
t_PLPH
22
t_PLIV
22
t_PXIX
22
t_PXIZ
22
t_AVIV
22
t_PLAZ
22
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
2t_CLCL–40
ns
t_CLCL–25
ns
t_CLCL–25
ns
4t_CLCL–75
ns
t_CLCL–25
ns
3t_CLCL–45
ns
3t_CLCL–70
ns
0
ns
t_CLCL–25
ns
5t_CLCL–85
ns
10
ns
t_RLRH
23, 24
t_WLWH
23, 24
t_RLDV
23, 24
t_RHDX
23, 24
t_RHDZ
23, 24
t_LLDV
23, 24
t_AVDV
23, 24
t_LLWL
23, 24
t_AVWL
23, 24
t_QVWX
23, 24
t_WHQX
23, 24
t_RLAZ
23, 24
t_WHLH
23, 24
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
RD low to address float
RD or WR high to ALE high
6t_CLCL–100
ns
6t_CLCL–100
ns
5t_CLCL–110
ns
0
ns
2t_CLCL–28
ns
8t_CLCL–150
ns
9t_CLCL–165
ns
3t_CLCL–50
3t_CLCL+50
ns
4t_CLCL–75
ns
t_CLCL–30
ns
t_CLCL–25
ns
0
ns
t_CLCL–25
t_CLCL+25
ns
t_CHCX
26
t_CLCX
26
t_CLCH
26
t_CHCL
26
Shift Register
High time
Low time
Rise time
Fall time
12
ns
12
ns
20
ns
20
ns
t_XLXL
25
Serial port clock cycle time
12t_CLCL
ns
t_QVXH
25
Output data setup to clock rising edge
10t_CLCL–133
ns
t_XHQX
25
Output data hold after clock rising edge
2t_CLCL–60
ns
t_XHDX
25
Input data hold after clock rising edge
0
ns
t_XHDV
25
Clock rising edge to input data valid
10t_CLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 80C32/52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0
drivers.
1998 May 01
28