80C575 Datasheet, PDF(23/40 Page) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

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80C575 Datasheet, PDF (23/40 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

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Philips Semiconductors

80C51 8-bit microcontroller family

8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

Product specification

80C575/83C575/

87C575

EC3TDC

EC2TDC

EC1TDC

EC0TDC EC3OD *

EC2OD * EC1OD *

EC0OD *

CMPE

(91H)

P1.0 / CMP0+

P1.1 / CMP0â

P3.5 / CMP1+

P3.6 / CMP2+

P3.7 / CMP3+

P3.4 / CMPRâ

ENABLE

TO CEX0 INPUT OF

PCA MODULE 0

TO CEX1 INPUT OF

PCA MODULE 1

TO CEX2 INPUT OF

PCA MODULE 2

TO CEX3 INPUT OF

PCA MODULE 3

P1.3 / CMP0

P1.4 / CMP1

P1.5 / CMP2

P1.6 / CMP3

* : WILL DISABLE PULLUPS

ON RELEVANT PINS

EC3DP *

EC2DP * EC1DP *

EC0DP *

C3R0

C2R0

Figure 21. Analog Comparators

C1R0

C0R0

CMP

(E8H)

SU00244

Reduced EMI Mode

There are two bits in the AUXR register that

can be set to reduce the internal clock drive

and disable the ALE output. AO (AUXR.0)

when set turns off the ALE output. LO

(AUXR.1) when set reduces the drive of the

internal clock circuitry. Both bits are cleared

on Reset. With LO set the 87C575 will still

operate at 12MHz, but will have reduced EMI

in the range above 100MHz.

AUXR (8EH)

ââ ââ ââ ââ ââ ââ LO AO

AO:

Turns off ALE output.

LO:

Reduces drive of internal clock

circuitry. 8XC575 specâd to 12MHz

when LO set.

INTERNAL RESET

Internal resets generated by the power on,

low voltage, and oscillator fail detect circuits

are self timed to guarantee proper

initialization of the 8XC575. Reset will be held

approximately 24 oscillator periods after

normal conditions are detected by all enabled

detect circuits. Internal resets do not drive

RST but will cause missing pulses on ALE.

Interrupt Enable (IE) Register

EA IE.7 enable all interrupts

EC IE.6 enable PCA interrupt

ET2 IE.5 enable Timer 2 interrupt

ES IE.4 enable Serial I/O interrupt

ET1 IE.3 enable Timer 1 interrupt

EX1 IE.2 enable External interrupt 1

ET0 IE.1 enable Timer 0 interrupt

EX0 IE.0 enable External interrupt 0

Interrupt Priority (IP) Register

IP.7 reserved

PPC IP.6 PCA interrupt priority

PT2 IP.5 Timer 2 interrupt priority

PS IP.4 Serial I/O interrupt priority

PT1 IP.3 Timer 1 interrupt priority

PX1 IP.2 External interrupt 1 priority

PT0 IP.1 Timer 0 interrupt priority

PX0 IP.0 External interrupt 0 priority

Priority Source Flag

1 INT0 IE0

2 Timer 0 TF0

3 INT1 IE1

4 Timer 1 TF1

Vector

03H highest priority

0BH

13H

1BH

87C575

5 PCA CF,CCFn 33H

6 Serial I/O RI,TI 23H

7 Timer 2 TF2/EXF2 2BH lowest priority

80C575/83C575/87C575

5 Serial I/O RI/TI 23H

6 Timer 2 TF2/EXF2 23H

7 PCA CF, CCFn 33H lowest priority

Power Control (PCON) Register

SMOD1 PCON.7 double baud rate bit

SMOD0 PCON.6 SCON.7 access control

OSF PCON.5 oscillator fail flag

POF PCON.4 power off flag

LVF

PCON.3 low voltage flag

GF0 PCON.2 general purpose flag

PCON.1 power down mode bit

IDL

PCON.0 idle mode bit

Port 2 Pullup Disable Register

1998 May 01

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