80C575 Datasheet, PDF (16/40 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer

Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM/ROMless, 4 comparator, failure detect circuitry, watchdog timer
Product specification
80C575/83C575/
87C575
CCAPnH
ENABLE
OVERFLOW
CCAPnL
0
8–BIT
COMPARATOR
CL < CCAPnL
CL >= CCAPnL
1
CL
PCA TIMER/COUNTER
CEXn
––
ECOMn CAPPn CAPNn MATn
TOGn
PWMn ECCFn
0
0
0
0
0
Figure 12. PCA PWM Mode
CCAPMn, n: 0..4
(DAH – DEH)
SU00752
Watchdog Detailed Operation
EPROM Device (and ROMless Operation:
EA = 0)
In the ROMless operation (ROM part, EA = 0)
and in the EPROM device, the watchdog
operates in the following manner (see
Figure 14).
Whether the watchdog is in the watchdog or
timer mode, when external RESET is applied,
the following takes place:
• Watchdog mode bit set to watchdog mode.
• Watchdog run control bit set to ON.
• Autoload register set to 00 (min. count).
• Watchdog time-out flag cleared.
• Prescaler is cleared.
• Prescaler tap set to the highest divide.
• Autoload takes place.
The watchdog can be fed even though it is in
the timer mode.
Note that the operational concept is for the
watchdog mode of operation, when coming
out of a hardware reset, the software should
load the autoload registers, set the mode to
watchdog, and then feed the watchdog
(cause an autoload). The watchdog will now
be starting at a known point.
If the watchdog is in the watchdog mode and
running and happens to underflow at the time
the external RESET is applied, the watchdog
time-out flag will be cleared.
When the watchdog is in the watchdog mode
and the watchdog underflows, the following
action takes place (see Figure 16):
• Autoload takes place.
• Watchdog time-out flag is set
• Mode bit unchanged.
• Watchdog run bit unchanged.
• Autoload register unchanged.
• Prescaler tap unchanged.
• All other device action same as external
reset.
Note that if the watchdog underflows, the
program counter will start from 00H as in the
case of an external reset. The watchdog
time-out flag can be examined to determine if
the watchdog has caused the reset condition.
The watchdog time-out flag bit can be cleared
by software.
When the watchdog is in the timer mode and
the timer software underflows, the following
action takes place:
• Autoload takes place.
• Watchdog time-out flag is set
• Mode bit unchanged.
• Watchdog run bit unchanged.
• Autoload register unchanged.
• Prescaler tap unchanged.
Mask ROM Device (EA = 1)
In the mask ROM device, the watchdog
mode bit (WDMOD) is mask programmed
and the bit in the watchdog command register
is read only and reflects the mask
programmed selection. If the mask
programmed mode bit selects the timer
mode, then the watchdog run bit (WDRUN)
operates as described under EPROM
Device. If the mask programmed bit selects
the watchdog mode, then the watchdog run
bit has no effect on the timer operation (see
Figure 15).
Watchdog Function
The watchdog consists of a programmable
prescaler and the main timer. The prescaler
derives its clock from the on-chip oscillator.
The prescaler consists of a divide by 12
followed by a 13 stage counter with taps from
stage 6 through stage 13. This is shown in
Figure 17. The tap selection is
programmable. The watchdog main counter
is a down counter clocked (decremented)
each time the programmable prescaler
underflows. The watchdog generates an
underflow signal (and is autoloaded) when
the watchdog is at count 0 and the clock to
decrement the watchdog occurs. The
watchdog is 8 bits long and the autoload
value can range from 0 to FFH. (The
autoload value of 0 is permissible since the
prescaler is cleared upon autoload).
This leads to the following user design
equations. Definitions :t_OSC is the oscillator
1998 May 01
16