83C576 Datasheet, PDF (33/46 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
Product specification
83C576/87C576
AC ELECTRICAL CHARACTERISTICS
T_amb = 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; V_CC = 5V ±10%, V_SS = 0V^{1, 2}
VARIABLE CLOCK
SYMBOL FIGURE
PARAMETER
MIN
MAX
UNIT
1/t_CLCL
25
Oscillator frequency: Speed Version
8XC576
E
6
16
MHz
OSCF
Oscillator fail detect frequency
0.6
5.5
MHz
TR
Comparator response time
10
µs
t_LHLL
25
t_AVLL
25
t_LLAX
25
t_LLIV
25
t_LLPL
25
t_PLPH
25
t_PLIV
25
t_PXIX
25
t_PXIZ
25
t_AVIV
25
t_PLAZ
25
Data Memory
ALE pulse width
Address valid to ALE low
Address hold after ALE low
ALE low to valid instruction in
ALE low to PSEN low
PSEN pulse width
PSEN low to valid instruction in
Input instruction hold after PSEN
Input instruction float after PSEN
Address to valid instruction in
PSEN low to address float
2t_CLCL–40
ns
t_CLCL–40
ns
t_CLCL–30
ns
4t_CLCL–100
ns
t_CLCL–30
ns
3t_CLCL–45
ns
3t_CLCL–105
ns
0
ns
t_CLCL–25
ns
5t_CLCL–105
ns
10
ns
t_RLRH
26, 27
t_WLWH
26, 27
t_RLDV
26, 27
t_RHDX
26, 27
t_RHDZ
26, 27
t_LLDV
26, 27
t_AVDV
26, 27
t_LLWL
26, 27
t_AVWL
26, 27
t_QVWX
26, 27
t_WHQX
26, 27
t_RLAZ
26, 27
t_WHLH
26, 27
External Clock
RD pulse width
WR pulse width
RD low to valid data in
Data hold after RD
Data float after RD
ALE low to valid data in
Address to valid data in
ALE low to RD or WR low
Address valid to WR low or RD low
Data valid to WR transition
Data hold after WR
RD low to address float
RD or WR high to ALE high
6t_CLCL–100
ns
6t_CLCL–100
ns
5t_CLCL–165
ns
0
ns
2t_CLCL–60
ns
8t_CLCL–150
ns
9t_CLCL–165
ns
3t_CLCL–50
3t_CLCL+50
ns
4t_CLCL–130
ns
t_CLCL–50
ns
t_CLCL–50
ns
0
ns
t_CLCL–40
t_CLCL+40
ns
t_CHCX
29
t_CLCX
29
t_CLCH
29
t_CHCL
29
Shift Register
High time
Low time
Rise time
Fall time
20
ns
20
ns
20
ns
20
ns
t_XLXL
28
Serial port clock cycle time
12t_CLCL
ns
t_QVXH
28
Output data setup to clock rising edge
10t_CLCL–133
ns
t_XHQX
28
Output data hold after clock rising edge
2t_CLCL–60
ns
t_XHDX
28
Input data hold after clock rising edge
0
ns
t_XHDV
28
Clock rising edge to input data valid
10t_CLCL–133
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. Interfacing the 83C576/87C576 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port
0 drivers.
1998 Jun 04
33