83C576 Datasheet, PDF(26/46 Page) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

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83C576 Datasheet, PDF (26/46 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

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Philips Semiconductors

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

Product specification

83C576/87C576

fOSC

INTERNAL

BUS

1/2

PWMP

REG

8-BIT

PRESCALER

8-BIT

COUNTER

PWM0

8-BIT

DETECT

OUTPUT

BUFFER

P2.6

PWM1

8-BIT

DETECT

Figure 23. Block Diagram of PWMs

OUTPUT

BUFFER

P2.7

SU00256A

PCA Interrupt System

The PCA on most 80C51 family devices provides a single interrupt

source, EC (IE.6). The 8xC576 expands the flexibility of the PCA by

providing additional interrupt sources for each of the five PCA

modules, EC0 (IE1.0) through EC4 (IE1.4), in addition to the original

interrupt source EC (IE.6). Any of these sources can be enabled at

any time. It is possible for both a module source (EC0 through EC4)

to be enabled at the same time that the single source, EC, is

enabled. In this case, a module event will generate an interrupt for

both the module source and the single source, EC.

Priority Source

1 INT0

2 ADC

3 TIMER 0

4 INT1

5 TIMER 1

6 SERIAL

7 PCA0

8 PCA1

9 PCA2

10 PCA3

11 PCA4

12 PCA

13 TIMER 2

14 UPI

15 UPI

Flag

IE0

ADF

TF0

IE1

TF1

RI,TI

CC0

CC1

CC2

CC3

CC4

ECF

TF2/EXF2

IBF

OBE

Vector

03H

3BH

0BH

13H

1BH

23H

43H

4BH

53H

5BH

63H

33H

2BH

6BH

73H

highest priority

lowest priority

Power Control (PCON) Register

SMOD1 PCON.7 double baud rate bit

SMOD0 PCON.6 SCON.7 access control

OSF

PCON.5 oscillator fail flag

POF

PCON.4 power off flag

LVF

PCON.3 low voltage flag

WDTOF PCON.2 watchdog timeout flag

PCON.1 power down mode bit

IDL

PCON.0 idle mode bit

UNIVERSAL PERIPHERAL INTERFACE

UPI mode allows the 8XC576 to function as a slave processor

connected to a host CPU bus via port 0. The interface consists of

port 0 input and output buffer registers and the UPI control/status

(UE) in the UCS. When operating in UPI mode, port 0 pins should

be programmed to High-Z (P0M1=1 and P0M2=0) by user firmware.

Access to port 0 is controlled by inputs WR, RD, CS, and A0. RD

and WR are the external read and write strobes controlled by the

host CPU. CS is the chip select input, normally a decoded address

from the host CPU bus, which qualifies RD and WR (these pins

have no effect when CS=1). The A0 pin is an address input from the

host CPU which selects either the port 0 output buffer or the UCS

operation, the value of the A0 pin is latched in the AF flag in the

UCS register. The following is a summary of the UPI data control

inputs:

CS RD WR A0

0 0 1 0 read port 0 output buffer,

clear OBF/set OBE

0 0 1 1 read UPI control/ status register

0 1 0 0 write data to input buffer set IBF, clear AF

0 1 0 1 write command to input buffer set IBF, AF

1 x x x disable input/output

UPI Control Status Register (UCS, Reset value = 00H)

UCS.7 ST7

User defined status bit

UCS.6 ST6

User defined status bit

UCS.5 ST5

User defined status bit

UCS.4 ST4

User defined status bit

UCS.3 UE

UPI Enable bit â if UE=1, UPI is enabled

(read only AF, IBF, and OBE/OBF), if UE=0,

UPI is disabled and port 0 functions

normally.

UCS.2 AF

Address Flag â contains status of the A0

(address) pin during the last write. If A0=0,

the input buffer should be interpreted as

data by the 8XC576 software, if A0=1, the

input buffer should be interpreted as a

command.

USC.1 IBF

Input Buffer Full flag â set by hardware on

trailing (rising) edge of WR when CS=0,

cleared by hardware when port 0 SFR is

read (by the 8XC576 software).

USC.0 OBE/OBF Output Buffer Full flag â set by hardware

during writes (by 8XC576 software) to the

port 0 SFR, set/cleared by hardware on the

trailing (rising) edge of RD when CS=0 and

A0=0.

NOTE: This bit is defined as OBE (1=empty) when read by the

MCU, and, as OBF (âfull) when read by the external host.

The IBF and OBF flag bits reflect the status of the input/output

buffers. The host CPU writes to the 8XC576 by driving data on the

external bus connected to port 0 and strobing the WR pin while

CS=0. The WR strobe latches port 0 data in the input buffer and

sets the IBF flag on the trailing (rising) edge. When the 8XC576

reads from port 0 in UPI mode, it reads from the input buffer and

1998 Jun 04

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