83C576 Datasheet, PDF (27/46 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
Product specification
83C576/87C576
clears the IBF. When the 8XC576 writes to port 0 in UPI mode, it
writes to the output buffer which sets the OBF and clears the OBE
flag. The host CPU can read the output buffer or the UCS register
enabling the port 0 drivers, the OBF flag is cleared and the OBE flag
is set when the output buffer is read.
When the UPI is enabled, the AF, IBF, and OBE/OBF flags are
read-only, and thus can only be modified by specific hardware
events.
The UPI runs in idle mode. It can interrupt the part out of Idle mode
for all UPI write and data read operations. It will not interrupt out of
idle mode for a UCS register read operation.
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an
inverting amplifier. The pins can be configured for use as an on-chip
oscillator, as shown in the Logic Symbol, page 4.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip
peripherals stay active. The instruction to invoke the idle mode is the
last instruction executed in the normal operating mode before the
idle mode is activated. The CPU contents, the on-chip RAM, and all
of the special function registers remain intact during this mode. The
idle mode can be terminated either by any enabled interrupt (at
which time the process is picked up at the interrupt service routine
and continued), or by a hardware reset which starts the processor in
the same manner as a power-on reset. Also see UPI section.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. The control
bits for the reduced power modes are in the special function register
PCON. Power-down mode can be terminated with either a hardware
reset or external interrupt. With an external interrupt INT0 or INT1
must be enabled and configured as level sensitive. Holding the pin
low restarts to oscillator and bringing the pin back high completes
the exit.
Power-down mode can be disabled by the DPD bit in the WDCON
register. Reset and waking up from power-down will also enable the
DPD bit, therefore, the DPD bit must be cleared again before the
power-down mode.
DESIGN CONSIDERATIONS
At power-on, the voltage on V_CC must come up with RST low for a
proper start-up.
Table 2 shows the state of I/O ports during low current operating
modes.
Table 2. External Pin Status During Idle and Power-Down Modes
MODE
PROGRAM MEMORY
ALE
PSEN
PORT 0
Idle
Internal
1
1
Data
Idle
External
1
1
Float
Power-down
Internal
0
0
Data
Power-down
External
0
0
Float
PORT 1
Data
Data
Data
Data
PORT 2
Data
Address
Data
Data
PORT 3
Data
Data
Data
Data
1998 Jun 04
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