83C576 Datasheet, PDF(23/46 Page) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

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83C576 Datasheet, PDF (23/46 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

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Philips Semiconductors

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,

failure detect circuitry, watchdog timer

Product specification

83C576/87C576

SM0

SM1

SM2

REN

TB8

RB8

SCON

(98H)

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

COMPARATOR

IN UART MODE 2 OR MODE 3 AND SM2 = 1:

INTERRUPT IF REN=1, RB8=1 AND âRECEIVED ADDRESSâ = âPROGRAMMED ADDRESSâ

â WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES

â WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

Figure 21. UART Multiprocessor Communication, Automatic Address Recognition

SU00045

CMP Register Bit Definitions

CMP.7 enable comparator 3

CMP.6 enable comparator 2

CMP.5 enable comparator 1,

CMP.4 enable comparator 0

CMP.3 comparator 3 output (read only)

CMP.2 comparator 2 output (read only)

CMP.1 comparator 1 output (read only)

CMP.0 comparator 0 output (read only)

All comparators are disabled automatically in power down mode. In

idle mode unused comparators should be disabled by software to

save power. A comparator can generate an interrupt that will

terminate idle mode when used to drive a PCA capture input.

The CMPE register contains bits to enable each comparator to drive

external output pins or internal PCA capture inputs. When the

comparator is configured for external output, the user must also

configure the output port in one of its output modes. The comparator

output is wire-ORed with the corresponding port SFR bit, so the

SFR bit must also be set by software to enable the output.

CMPE Register Bit Definitions

CMPE.7 enables comparator 3 to drive CEX3

CMPE.6 enables comparator 2 to drive CEX2

CMPE.5 enables comparator 1 to drive CEX1

CMPE.4 enables comparator 0 to drive CEX0

CMPE.3 enables comparator 3 output on P2.3

CMPE.2 enables comparator 2 output on P2.2

CMPE.1 enables comparator 1 output on P2.1

CMPE.0 enables comparator 0 output on P2.0

When 1s are written to CMPE bits 7-4, the comparator outputs will

drive the corresponding capture input. When 1s are written to CMPE

bits 3-0 the comparator output will also drive the corresponding

port 2 pin. If the comparatorâs enabled to drive the capture input but

not the port pin, then the port pin can be used for general purpose

I/O. When a comparator output is enabled, the user will need to

configure the port for one of its output modes.

There are two special function registers associated with the

comparators. They are CMP which contains the comparator enables

and a bit that can be read by software to determine the state of each

comparatorâs output, and CMPE which controls whether the output

from each comparator drives the associated output pin or a capture

input associated with one of the PCA modules.

The CMP registers bits 0â3 can be read by software to determine

the state of the output of each comparator. To do this the associated

comparator must be enabled but the output in port 2 can be

disabled. This allows easy polling of the comparator output value

without the need to use up a port pin.

The CMPE register allows the comparator to drive the associated

PCA module capture input, so that on compare a capture can be

generated in the PCA. Bits 0â3 of this register enable the

comparator output to drive the associated port 2 output circuitry.

Used as a comparator output, the output mode for this port must be

configured for output by the user and the port output SFR bit latch

must be set. If the comparator is not enabled to drive the port 2

circuitry, the associated port 2 pin can be used for other I/O. This

includes when a comparator is enabled to drive the capture input to

a PCA module.

Reduced EMI Mode

There are two bits in the AUXR register that can be set to reduce

the internal clock drive and disable the ALE output. AO (AUXR.0)

when set turns off the ALE output. LO (AUXR.1) when set reduces

the drive of the internal clock circuitry. Both bits are cleared on

Reset. With LO set the 8XC576 will still operate at 12MHz, and will

have reduced EMI in the range above 100MHz.

8XC576 Reduced EMI Mode

AUXR (0X8E)

ââ

RST

TXI

AO: Turns off ALE output.

LO: Reduces drive of internal clock circuitry. 8XC576 specâd to

12MHz when LO set.

TXI: Inverts TxD when set.

RST: Software reset.

1998 Jun 04

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