83C576 Datasheet, PDF (25/46 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
Product specification
83C576/87C576
PWMs
The pulse width modulator system of the 8XC576 contains two
PWM output channels. These channels generate pulses of
programmable length and interval. The prescaler and counter are
common to both PWM channels.
The prescaler is loaded with the complement of the PWMP register
during counter overflow, internal reset, and when EN/CLR# = 0. The
repetition frequency is defined by the 8-bit prescaler which clocks
the counter. The prescaler division factor = PWMP+1. Reading the
PWMP gives the current reload value. The actual count of the
prescaler cannot be read.
The 8-bit counter counts from 0–254 inclusive. The value of the
counter is compared to the contents of the compare registers PWM0
and PWM1. When the counter compares to the compare register,
that register’s output goes LOW. When the counter reaches zero the
output is set HIGH unless PWMn = 00H. The duty cycle of each
channel is defined by the contents of its compare register and is in
the range of 0 to 1, programmed in increments of 1/255.
The outputs can be set continuously low by loading PWMn with 00H
and continuously high by loading with FFH.
The PWM counter is enabled with bit EN/CLR# of the PWCON
register. Output to the port pin is separately enabled by setting the
PWEn bits in the PWCON register. The counter remains active if
EN/CLR# is set even if both PWEn bits are reset. The PWM function
is reset by a chip reset. In idle mode, the PWM will function as
configured by PWCON. In power-down the state of the PWM will
freeze when the internal clock stops. If the chip is awakened with an
external interrupt, the PWM will continue to function from its state
when power-down was entered. The EN/CLR# bit of PWCON will
clear the counter and load the contents of the PWMP into the
prescaler when set LOW. If PWEn is set at this time the output will
go HIGH unless PWMn is 00H.
The repetition frequency is given by:
f_PWM + ₍₅₁₀
f_OSC
(1 ) PWMP))
An oscillator frequency of 12MHz results in a repetition range of
92Hz to 23.5KHz.
The high/low ratio of PWMn is PWMn/(255–PWMn) for PWMn
values except 255. A PWMn value of 255 results in a high PWMn
output.
In order for the PWMn output to be used as a standard I/O pin,
PWMn must be reset. The PWM counter can still be used as an
internal timer by setting EN/CLR#.
Pulse Width Modulator Control Register Bit Definitions
(PWCON = BCH)
PWMF PWCON.3 Counter overflow flag,
must be cleared by software
EN/CLR PWCON.2 Counter enable and counter/prescaler
reset when Low
PWE1 PWCON.1 PWM1 output to P2.7 pin enable
PWE0 PWCON.0 PWM0 output to P2.6 pin enable
Auxiliary Register Bit Definitions (AUXR =8EH)
RST AUXR.3 Software reset bit
TXI AUXR.2 SIO TxD invert
LO AUXR.1 Low Speed, reduces internal clock drive
AO AUXR.0 ALE Off, when set turns off ALE
Interrupt Enable 0 (IE0) Register
EA IE0.7 Enable all interrupts
EC IE0.6 Enable PCA interrupt
ET2 IE0.5 Enable Timer 2 interrupt
ES IE0.4 Enable Serial I/O interrupt
ET1 IE0.3 Enable Timer 1 interrupt
EX1 IE0.2 Enable External interrupt 1
ET0 IE0.1 Enable Timer 0 interrupt
EX0 IE0.0 Enable External interrupt 0
Interrupt Enable 1 (IE1) Register
EOB IE1.7 Enable OBE interrupt
EIB IE1.6 Enable IBF interrupt
EAD IE1.5 Enable ADC interrupt
EC4 IE1.4 Enable PCA module 4 interrupt
EC3 IE1.3 Enable PCA module 3 interrupt
EC2 IE1.2 Enable PCA module 2 interrupt
EC1 IE1.1 Enable PCA module 1 interrupt
EC0 IE1.0 Enable PCA module 0 interrupt
Interrupt Priority 0 (IP0) Register
IP0.7 (reserved)
PPC IP0.6 PCA interrupt priority
PT2 IP0.5 Timer 2 interrupt priority
PS IP0.4 Serial I/O interrupt priority
PT1 IP0.3 Timer 1 interrupt priority
PX1 IP0.2 External interrupt 1 priority
PT0 IP0.1 Timer 0 interrupt priority
PX0 IP0.0 External interrupt 0 priority
Interrupt Priority 1 (IP1) Register
POB IP1.7 OBE interrupt priority
PIB IP1.6 IBF interrupt priority
PAD IP1.5 ADC interrupt priority
PC4 IP1.4 PCA module 4 interrupt priority
PC3 IP1.3 PCA module 3 interrupt priority
PC2 IP1.2 PCA module 2 interrupt priority
PC1 IP1.1 PCA module 1 interrupt priority
PC0 IP1.0 PCA module 0 interrupt priority
1998 Jun 04
25