83C576 Datasheet, PDF (30/46 Pages) NXP Semiconductors – 80C51 8-bit microcontroller family 8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

Philips Semiconductors
80C51 8-bit microcontroller family
8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators,
failure detect circuitry, watchdog timer
Product specification
83C576/87C576
DC ELECTRICAL CHARACTERISTICS
T_amb = 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; V_CC = 5V ±10%, V_SS = 0V
TEST
SYMBOL
PARAMETER
CONDITIONS
LIMITS
MIN
TYP¹
MAX
UNIT
V_IL
V_IL1
V_IL2
V_IH
V_IH1
HYS
Input low voltage (except Port 1, EA)
Input low voltage (EA)
Input low voltage (Port 1)
Input high voltage (except Port 1, XTAL1, RST)
Input high voltage (XTAL1, RST, Port 1)
Hysteresis voltage (Port 1)
I_IH < 2mA
I_IH < 2mA
–0.5
–0.5
–0.5
0.2V_CC+0.9
0.7V_CC
200
0.2V_CC–0.1
V
0.2V_CC–0.45
V
0.3V_CC
V
V_CC+0.5
V
V_CC+0.5
V
mV
V_OL
V_OL1
Output voltage low (Ports 1, 2, 3)
Output voltage low (Ports 0, ALE, PSEN⁾
I_OL = 1.6mA
I_OL = 3.2mA
V_OH
Output voltage high (Ports 1, 2, 3 in push-pull mode)
I_OH = –1.6mA
V_CC–1.0
V_OH1
Output voltage high (Port 0, ALE, PSEN)
I_OH = –3.2mA
V_CC–0.7
V_OH2
Output voltage high in weak pullup mode (Port 0, 2, 3)
I_OH = –10µA
V_CC–1.0
V_IO
Offset voltage comparator inputs
–35
V_CR
Common mode range comparator inputs
0
I_IL
Logical 0 input current (Ports 0, 2, 3) (weak pull-up)
V_IN = 0.45V
I_IH
Input pulldown current (Port 0, Port2 in open drain mode) 0.45 < V_IN < V_CC
2
I_L2
Input leakage current (EA, P0. 2. 3 High-Z)
0.45 < V_IN < V_CC
–10
I_LA
Input leakage current comparator/ADC inputs
I_CC
Power supply current:⁷
Active mode @ 16MHz⁵
Idle mode @ 16MHz
Power-down mode
0 < V_IN < V_CC
–1.0
See note 6
20
8
5
0.45
V
0.45
V
V
V
V
+35
mV
V_CC
V
–250
µA
40
µA
+10
µA
+1.0
µA
30
mA
12
mA
75
µA
R_RST
Internal reset pull-up resistor
V_IN = 0V
50
200
kΩ
V_LOW
Low V_CC detect voltage
3.75
4.25
V
C_IO
Pin capacitance⁹
f = 1MHz
15
pF
NOTES:
1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V_OLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I_OL can exceed these conditions provided that no
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
3. Capacitive loading on ports 0 and 2 may cause the V_OH on ALE and PSEN to momentarily fall below the 0.9V_CC specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V_IN is between V_IH and V_IL.
5. I_CCMAX at other frequencies can be determined from Figure 33.
6. See Figures 34 through 37 for I_CC test conditions.
7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
8. Under steady state (non-transient) conditions, I_OL must be externally limited as follows:
Maximum I_OL per port pin:
10mA
Maximum I_OL per 8-bit port:
26mA
Maximum total I_OL for all outputs: 71mA
If I_OL exceeds the test condition, V_OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
9. 20pF MAX for CERDIP package; 15pF MAX for all other packages.
1998 Jun 04
30