TDA8596_15 Datasheet, PDF (30/48 Pages) NXP Semiconductors – I2C-bus controlled 4 ´ 45 W power amplifier with symmetrical inputs

NXP Semiconductors
TDA8596
I²C-bus controlled 4 × 45 W power amplifier with symmetrical inputs
Table 17. Characteristics …continued
Refer to test circuit (see Figure 29) at V_P = 14.4 V; R_L = 4 Ω; f = 1 kHz; R_S = 0 Ω; normal mode; unless otherwise specified.
Tested at T_amb = 25 °C; guaranteed for T_amb = −40 °C to +105 °C.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
t_{d(mute_off)}
mute off delay time mute to 10 % of output signal;
I_LO(SVR) = 0 µA
I²C-bus mode (IB1[D0]); with
[3] ₂₉₅
465
795
ms
I_LO(SVR) = 10 µA → +15 ms; no
DC load (IB1[D1] = 0); low pop
disabled (IB2[D3] = 1); see Figure 3
I²C-bus mode (IB1[D0]); with
[3] ₅₀₀
640
940
ms
I_LO(SVR) = 10 µA → +20 ms; DC load
active (IB1[D1] = 1); low pop disabled
(IB2[D3] = 1); see Figure 4
I²C-bus mode (IB1[D0]); with
[3] ₆₄₀
830
1190 ms
I_LO(SVR) = 10 µA → +20 ms; DC load
active (IB1[D1] = 0); low pop enabled
(IB2[D3] = 0); see Figure 5
legacy mode; with I_LO(SVR) = 10 µA → ^[3] 430
650
1030 ms
+20 ms; V_STB = 7 V; R_ADSEL = 0 Ω;
see Figure 6
t_{amp_on}
amplifier on time
amplifier from mute to 90 % of output
signal; I_LO(SVR) = 0 µA
I²C-bus mode (IB1[D0]); with
[3] ₃₆₀
520
870
ms
I_LO(SVR) = 10 µA → +30 ms; no
DC load (IB1[D1] = 0); low pop
disabled (IB2[D3] = 1); see Figure 3
I²C-bus mode (IB1[D0]); with
[3] ₅₆₅
695
1015 ms
I_LO(SVR) = 10 µA → +35 ms; DC load
active (IB1[D1] = 1); low pop disabled
(IB2[D3] = 1); see Figure 4
I²C-bus mode (IB1[D0]); with
[3] ₇₁₀
890
1270 ms
I_LO(SVR) = 10 µA → +30 ms; DC load
active (IB1[D1] = 0); low pop enabled
(IB2[D3] = 0); see Figure 5
legacy mode; with I_LO(SVR) = 10 µA → ^[3] 510
720
1120 ms
+20 ms; V_STB = 7 V; R_ADSEL = 0 Ω;
see Figure 6
t_off
amplifier switch-off time to DC output voltage < 0.1 V;
time
I²C-bus mode (IB1[D0]); I_LO(SVR) = 0 µA
with I_LO(SVR) = 10 µA → +0 ms; low
pop enabled (IB2[D3] = 0); see
[3] ₁₂₀
245
530
ms
Figure 4
with I_LO(SVR) = 10 µA → +0 ms; low
pop disabled (IB2[D3] = 1); see
Figure 5
[3] ₁₄₀
280
620
ms
t_d(mute-on)
mute to on delay time from 10 % to 90 % of output signal;
IB2[D1] = 1 to 0; V_i = 50 mV; see
Figure 6
-
20
40
ms
t_{d(soft_mute)}
soft mute delay time
from 10 % to 90 % of output signal;
IB2[D1] = 0 to 1; V_i = 50 mV; see
Figure 6
-
20
40
ms
TDA8596_2
Product data sheet
Rev. 02 — 8 November 2007
© NXP B.V. 2007. All rights reserved.
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