TDA8596_15 Datasheet, PDF (17/48 Pages) NXP Semiconductors – I2C-bus controlled 4 ´ 45 W power amplifier with symmetrical inputs

NXP Semiconductors
TDA8596
I²C-bus controlled 4 × 45 W power amplifier with symmetrical inputs
Table 4. Diagnostic information per pin for various modes …continued
Diagnostic
information
I²C-bus mode
Pin DIAG
Pin STB
Legacy mode
Pin DIAG
Temperature pre-
can be enabled
no
warning
yes; pre-warning level
is 145 °C
Short
can be enabled
no
yes
Speaker protection
can be enabled
no
yes
(missing current)
Offset detection
no
no
no
Load detection
no
no
no
Overvoltage
yes
no
yes
7.12 Offset detection
Offset detection can be performed either with or without input signal (for instance when
the DSP is in mute after a start-up). Assume the amplifier is in I²C-bus mode. When an
I²C-bus read of the output offset is performed the DBx[D2] latch will be set. When the
amplifier BTL output voltage crosses the 1.55 V window threshold within 1 s after a read is
performed, the DBx[D2] latch is reset and setting is disabled. After a certain delay, the
next read can be performed.
Example: in case the offset bits are still set when a successive read is performed more
than 1 s after the previous read, the output signal has not been within the offset window
thresholds for at least 1 s. This could either indicate an output signal with a frequency
below 1 Hz or the presence of an output offset above 1.55 V (see Figure 11).
I²C-bus mode only
V_O = V_OUT+ − V_OUT−
offset
threshold
reset:
setting
disabled
t
t = 1 s:
read = no offset
DB1 bit D2 reset
V_O = V_OUT+ − V_OUT−
offset
threshold
read = set bit
Fig 11. Offset detection
t
t = 1 s:
read = offset
DB1 bit D2 set
001aad175
TDA8596_2
Product data sheet
Rev. 02 — 8 November 2007
© NXP B.V. 2007. All rights reserved.
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