TDA8752A Datasheet, PDF (3/36 Pages) NXP Semiconductors – Triple high-speed Analog-to-Digital Converter ADC

Philips Semiconductors
Triple high-speed Analog-to-Digital
Converter (ADC)
Product specification
TDA8752A
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
V_CCA
V_DDD
V_CCD
V_CCO
V_CCA(PLL)
V_CCO(PLL)
I_CCA
I_DDD
I_CCD
I_CCO
analog supply voltage
logic supply voltage
digital supply voltage
output stages supply voltage
analog PLL supply voltage
output PLL supply voltage
analog supply current
logic supply current
digital supply current
output stages supply current
for R, G and B channels 4.75
for I²C-bus and 3-wire 4.75
4.75
for R, G and B channels 4.75
4.75
4.75
−
for I²C-bus and 3-wire −
−
f_CLK = 100 MHz;
−
ramp input
I_CCA(PLL)
I_CCO(PLL)
f_CLK
analog PLL supply current
output PLL supply current
maximum clock frequency
−
−
TDA8752A/6
60
TDA8752A/8
100
f_ref(PLL)
f_VCO
INL
DNL
∆G_amp/T
B
t_set
DR_PLL
P_tot
j_PLL(rms)
PLL reference clock frequency
VCO output clock frequency
DC integral non linearity
DC differential non linearity
amplifier gain stability as a function of
temperature
amplifier bandwidth
settling time of the ADC block plus AGC
PLL divider ratio
total power consumption
maximum PLL phase jitter (RMS value)
15
12
from analog input to
−
digital output; full-scale;
ramp input;
f_CLK = 100 MHz
from analog input to
−
digital output; full-scale;
ramp input;
f_CLK = 100 MHz
V_ref = 2.5 V with
−
100 ppm/°C maximum
−3 dB; T_amb = 25 °C
250
input signal settling
−
time < 1 ns; T_amb = 25 °C
100
f_CLK = 100 MHz;
−
ramp input
f_ref = 66.67 kHz;
−
f_CLK = 100 MHz
TYP.
5.0
5.0
5.0
5.0
5.0
5.0
120
1.0
40
6
28
5
−
−
−
−
±0.5
±0.5
−
−
−
−
1.0
0.3
MAX.
5.25
5.25
5.25
5.25
5.25
5.25
−
−
−
−
UNIT
V
V
V
V
V
V
mA
mA
mA
mA
−
mA
−
mA
−
MHz
−
MHz
280 kHz
100 MHz
±1.5 LSB
±1.0 LSB
200 ppm/°C
−
MHz
6
ns
4 095
−
W
−
ns
1999 Feb 24
3