TDA8752A Datasheet, PDF (27/36 Pages) NXP Semiconductors – Triple high-speed Analog-to-Digital Converter ADC

Philips Semiconductors
Triple high-speed Analog-to-Digital
Converter (ADC)
Product specification
TDA8752A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
I²C-bus; see note 3
f_SCL
clock frequency
t_BUF
time the bus must be free
before new transmission can
start
t_HD;STA
start condition hold time
t_SU;STA
start condition set-up time
t_CKL
LOW-level clock period
t_CKH
HIGH-level clock period
t_SU;DAT
data set-up time
t_HD;DAT
data hold time
t_r
SDA and SCL rise time
t_f
SDA and SCL fall time
t_SU;STOP
stop condition set-up time
C_L(bus)
capacitive load for each bus
line
repeated start
for f_SCL = 100 kHz
for f_SCL = 100 kHz
0
−
4.7 −
4.0 −
4.7 −
4.7 −
4.0 −
250 −
0
−
−
−
−
−
4.0 −
−
−
100
kHz
−
µs
−
µs
−
µs
−
µs
−
µs
−
ns
−
ns
1.0
µs
300
ns
−
µs
400
pF
Notes
1. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8000 acquisition points per equivalent
fundamental period. The calculation takes into account all harmonics and noise up to half clock frequency (NYQUIST
frequency). Conversion-to-noise ratio: S/N = EB × 6.02 + 1.76 dB.
2. Output data acquisition is available after the maximum delay time t_d(o), which is the time during which the data is
available. All the timings are given for a 10 pF capacitive load. A higher load can be used but the timing must then
be rechecked.
3. The I²C-bus timings are given for a frequency of 100 kbit/s (100 kHz). This bus can be used at a frequency of
400 kbit/s (400 kHz).
handbook, full pagewidth
CKADCO
tCPH
n
tCPL
50 % = 1.4 V
DATA
R0 to R7, ROR
G0 to G7, GOR
B0 to B7, BOR
VlN
td(o)
In _{− 1}
In
td(s)
In _{+ 1}
th(o)
In _{+ 2}
sample N + 1
sample N
sample N + 2
Fig.11 Timing diagram.
2.4 V
1.4 V
0.4 V
MGL103
1999 Feb 24
27