TDA8752A Datasheet, PDF (25/36 Pages) NXP Semiconductors – Triple high-speed Analog-to-Digital Converter ADC

Philips Semiconductors
Triple high-speed Analog-to-Digital
Converter (ADC)
Product specification
TDA8752A
SYMBOL
PARAMETER
CONDITIONS
MIN.
t_COAST(max)
t_recap
t_cap
Φ_step
maximum coast mode time
PLL recapture time
PLL capture time
phase shift step
−
when coast mode is aborted −
in start-up conditions
−
T_amb = 25 °C
−
ADCs
f_s
INL
DNL
ENOB
maximum sampling frequency TDA8752A/6
60
TDA8752A/8
100
DC integral non linearity
DC differential non linearity
effective number of bits
from IC analog input to
−
digital output; ramp input;
f_CLK = 100 MHz
from IC analog input to
−
digital output; ramp input;
f_CLK = 100 MHz
from IC analog input to
−
digital output; 10 kHz sine
wave input; ramp input;
f_CLK = 100 MHz; note 1
Signal-to-noise ratio
S/N
signal-to-noise ratio
maximum gain;
−
f_CLK = 100 MHz
minimum gain;
−
f_CLK = 100 MHz
Spurious free dynamic range
SFDR
spurious free dynamic range maximum gain;
−
f_CLK = 100 MHz
minimum gain;
−
f_CLK = 100 MHz
Clock timing output (CKADCO, CKBO and CKAO)
η_ext
ADC clock duty cycle
100 MHz output
45
f_CLK(max)
maximum clock frequency
100
Clock timing input (CKEXT)
f_CLK(max)
t_CPH
t_CPL
t_d(CLKO)
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
delay from CKEXT to
CKADCO
INV set to LOW
INV set to HIGH
100
3.6
4.5
13.6
−
TYP.
−
3
−
11.25
MAX.
40
−
5
−
−
−
−
−
±0.5
±1.5
±0.5
±1.0
7.4
−
45
−
44
−
60
−
60
−
50
55
−
−
−
−
−
−
−
−
14.7
15.2
−
14.7 + -t-^C---2-^L---^K-
UNIT
lines
lines
ms
deg
MHz
MHz
LSB
LSB
bits
dB
dB
dB
dB
%
MHz
MHz
ns
ns
ns
ns
1999 Feb 24
25