TDA8752A Datasheet, PDF (29/36 Pages) NXP Semiconductors – Triple high-speed Analog-to-Digital Converter ADC

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Table 13 Examples of PLL settings and performance; note 1
VIDEO
STANDARDS
CGA: 640 × 200
VGA: 640 × 480
VESA: 800 × 600
VESA: 1024 × 768
SUN: 1152 × 900
f_ref (kHz)
f_CLK
(MHz)
N
15.75
31.5
48.08
60.02
66.67
14.3 912
25.2 800
50 1040
78.8 1312
100 1500
KO
(MHz/V)
15
30
60
100
100
CZ
(nF)
CP
(nF)
I_P (µA)
Z
(kΩ)
LONG TIME JITTER⁽²⁾
ps (RMS) ns (p-p)
PLL PHASE DRIFT⁽³⁾
(ns)
150 1 200 4
−
−
1.2
150 1 400 2
610
3.6
0.7
150 1 700 1
480
2.9
0.55
150 1 700 1
380
2.3
0.3
150 1 700 1
360
2.2
0.3
Notes
1. Values measured at V_CCA = V_DDD = V_CCD = V_CCO = 5 V and T_amb = 25°C.
2. PLL long-term time jitter is measured at the end of the video line, where it is at its maximum.
3. Measured between 0 and 70 °C.