TDA8752A Datasheet, PDF (12/36 Pages) NXP Semiconductors – Triple high-speed Analog-to-Digital Converter ADC

Philips Semiconductors
Triple high-speed Analog-to-Digital
Converter (ADC)
Product specification
TDA8752A
Phase-locked loop
The ADCs are clocked either by an internal PLL locked to
the CKREF clock, (all of the PLL is on-chip except the loop
filter capacitance) or an external clock, CKEXT. Selection
is performed via the serial interface bus.
The reference clock (CKREF) range is between
15 and 280 kHz. Consequently, the VCO minimum
frequency is 12 MHz and the maximum frequency
100 MHz for the TDA8752A/8 and 60 MHz for the
TDA8752A/6. The gain of the VCO part can be controlled
via the serial interface, depending on the frequency range
to which the PLL is locked.
To increase the bandwidth of the PLL, the charge pump
current, controlled by the serial interface, must also be
increased. The relationship between the frequency and
the current is given by the following equation:
f_n = _2--1--π-- --₍--C-----_z---K--₊--^O---C-I--^P-_P-----₎----N--
Where:
f_n = the natural PLL frequency
K_O = the VCO gain
N = the division number
C_z and C_P = capacitors of the PLL filter.
The other PLL equation is as follows:
f_z
=
2----π^-----×^{-----R1------}×^-----C----_z^-
and

ξ

=
12--
×
-ff-ⁿ-_z



Where:
f_z = loop filter zero frequency
R = the chosen resistance for the filter
ξ = the damping factor.
Different resistances for the filter can be programmed via
the serial interface. To have better performances, the PLL
parameters should be chosen so that:
f_n/f_ref ≅ 0.05
ξ ≅ 1.5.
It is possible to control (independently) the phase of the
ADC clock and the phase of an additional clock output
(which could be used to drive a second TDA8752A).
For this, two serial interface-controlled digital phase-shift
controllers are included (controlled by 5-bit registers,
phase shift controller steps are 11.25° each on the whole
PLL frequency range).
CKREF is resynchronized, by the synchro block, on the
CKAO clock. The output is CKREFO (LOW during 8 clock
periods). CKAO is the clock at the output of the phase
selector A. This clock can be used as the clocks for CKBO
and CKADCO. The timing is given in Fig.5.
The COAST pin is used to disconnect the PLL phase
frequency detector during the frame flyback or the
unavailability of the CKREF signal. This signal can
normally be derived from the VSYNC signal.
The clock output is able to drive an external 10 pF load
(for the on-chip ADCs).
The PLL can be used in three different methods:
1. The IC can be used as stand-alone with a sampling
frequency of up to 100 MHz for the TDA8752A/8 and
up to 60 MHz for the TDA8752A/6.
2. When an RGB signal is at a pixel frequency exceeding
100 to 200 MHz, it is possible to follow one of the two
possibilities given below:
a) Using one TDA8752A; the sampling rate can be
reduced by a factor of two, by sampling the even
pixels in the even frame and the odd pixels in the
odd frame. The INV pin is used to toggle between
frames.
b) Using two TDA8752As the PLL of the master
TDA8752A is used to drive both ADC clocks.
The PLL of the slave TDA8752A is disconnected
and the CKBO of the master TDA8752A is
connected to pin CKEXT of both TDA8752A.
The master TDA8752A is used to sample the even
pixels and the slave TDA8752A for odd pixels,
using a 180° phase shift between the clocks
(CKADCO pins). The master chip has its INV pin
LOW while the slave chip has its INV pin HIGH,
which guarantees the 180° shift ADC clock drive.
It is then necessary to adjust phase B of the master
chip. Special care should be taken with the quality
of the input signal (input setting time).
If CKREFO output signal at the master chip is
needed, it is possible to use one of the two phase A
values in order to avoid set-up and hold problems
in the SYNCHRO function; e.g.
PHASEA = 100000 and PHASEA = 111111.
1999 Feb 24
12