TDA8752A Datasheet, PDF (20/36 Pages) NXP Semiconductors – Triple high-speed Analog-to-Digital Converter ADC

Philips Semiconductors
Triple high-speed Analog-to-Digital
Converter (ADC)
Product specification
TDA8752A
Table 8 Phase registers bits
Pa4 AND Pb4
0
0
↓
↓
1
1
Pa3 AND Pb3
0
0
↓
↓
1
1
Pa2 AND Pb2
0
0
↓
↓
1
1
Pa1 AND Pb1
0
0
↓
↓
1
1
Pa0 AND Pb0
0
1
↓
↓
0
1
PHASE SHIFT (°)
0
11.25
↓
↓
337.5
348.75
The default programmed value is as follows:
• No external clock: CKA at logic 0
• No use of the second clock: CKB at logic 0
• Phase shift for CKAO and CKADCO = 0°
• Phase shift for CKBO = 0°.
I²C-bus protocol
Table 9 I²C-bus address
A7
A6
A5
A4
1
0
0
1
A3
A2
A1
A0
1
ADD2
ADD1
0
The I²C-bus address of the circuit is 10011 xx0.
Bits A2 and A1 are fixed by the potential on pins ADD1 and ADD2. Thus, four TDA8752As can be used on the same
system, using the addresses for ADD1 and ADD2 with the I²C-bus. The A0 bit must always be equal to logic 0 because
it is not possible to read the data in the register. The timing and protocol for the I²C-bus are standard. Two sequences
are available, see Tables 10 and 11.
Table 10 Address sequence for mode 0; note 1
S IC ADDRESS ACK SUBADDRESS ACK
DATA
ACK SUBADDRESS ACK to P
REGISTER1
REGISTER1
REGISTER2
(see Table 1)
Note
1. Where: S = START condition, ACK = acknowledge and P = STOP condition.
Table 11 Address sequence for mode 1; note 1
S IC ADDRESS ACK SUBADDRESS ACK
DATA
ACK
DATA
ACK to P
xxx1 1111
REGISTER1
REGISTER2
(see Table 1)
Note
1. Where: S = START condition, ACK = acknowledge and P = STOP condition.
1999 Feb 24
20