TDA8752A Datasheet, PDF (24/36 Pages) NXP Semiconductors – Triple high-speed Analog-to-Digital Converter ADC

Philips Semiconductors
Triple high-speed Analog-to-Digital
Converter (ADC)
Product specification
TDA8752A
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
G_FINE
fine gain correction range
∆G_amp/T
I_GC
t_stab
V_i(p-p)
t_r(Vi)
t_f(Vi)
G_E(rms)
amplifier gain stability as a
function of temperature
gain current
amplifier gain adjustment
speed
input voltage range
(peak-to-peak value)
input voltage rise time
input voltage fall time
channel-to-channel gain
matching (RMS value)
fine register input code = 0; −
(see Fig.9)
fine register input
−
code = 31; (see Fig.9)
V_ref = 2.5 V with
−
100 ppm/°C maximum
variation
−
HSYNC active; capacitors −
on pins 8, 16 and 24 = 22 nF
corresponding to full-scale 0.4
output
f_i = 100 MHz; square wave −
f_i = 100 MHz; square wave −
maximum coarse gain;
−
T_amb = 25 °C
minimum coarse gain;
−
T_amb = 25 °C
0
−0.5
−
±20
25
−
−
−
1
2
Clamps
P_CLP
t_COR1
t_COR2
t_W(CLP)
CLP_E
A_off
precision
black level noise on RGB −1
channels = 10 mV (max.)
(RMS value); T_amb = 25 °C
clamp correction time to within ±100 mV black level input −
±10 mV
variation; clamp
capacitor = 4.7 nF
clamp correction time to less ±100 mV black level input −
than 1 LSB
variation; clamp
capacitor = 4.7 nF
clamp pulse width
500
channel-to-channel clamp
−1
matching
code clamp reference
clamp register input
−
code = 0
clamp register input
−
code = 255
−
−
−
−
−
−63.5
64
Phase-locked loop
j_PLL(rms)
long term PLL jitter
(RMS value)
DR
divider ratio
f_CLK = 60 MHz; see Table 13 −
450
f_CLK = 100 MHz;
see Table 13
−
360
100 −
f_ref
reference clock frequency
range
f_PLL
output clock frequency range
15
−
12
−
MAX. UNIT
−
dB
−
dB
200
ppm/°C
−
µA
−
mdB/µs
1.2
V
2.5
ns
2.5
ns
−
%
−
%
+1
LSB
300
ns
10
lines
2000 ns
+1
LSB
−
LSB
−
LSB
−
ps
−
ps
4 095
280
kHz
100
MHz
1999 Feb 24
24