TDA8752A Datasheet, PDF (18/36 Pages) NXP Semiconductors – Triple high-speed Analog-to-Digital Converter ADC

Philips Semiconductors
Triple high-speed Analog-to-Digital
Converter (ADC)
Product specification
TDA8752A
OFFSET REGISTER
This register controls the clamp level for the
RGB channels. The relationship between the
programming code and the level of the clamp code is given
in Table 2.
Table 2 Coding
PROGRAMMED
CODE
0
1
2
↓
127
↓
254
255
CLAMP CODE
−63.5
−63
−62.5
↓
0
↓
63.5
64
ADC OUTPUT
underflow
0
↓
63 or 64
64
The default programmed value is:
• Programmed code = 127
• Clamp code = 0
• ADC output = 0.
Table 3 Gain correspondence (COARSE)
N_COARSE
32
99
GAIN
0.825
2.5
V_i TO BE
FULL-SCALE
1.212
0.4
The default programmed value is as follows:
• N_COARSE = 32
• Gain = 0.825
• V_i to be full-scale = 1.212.
To modulate this gain, the fine register is programmed
using the above equation. With a full-scale ADC input, the
fine register resolution is a ¹â„₂LSB peak-to-peak
(see Table 4 for N_COARSE = 32).
Table 4 Gain correspondence (FINE)
N_FINE
0
31
GAIN
0.825
0.878
V_i TO BE
FULL-SCALE
1.212
1.139
The default programmed value is: N_FINE = 0.
COARSE AND FINE REGISTERS
These two registers enable the gain control, the AGC gain
with the coarse register and the reference voltage with the
fine register. The coarse register programming equation is
as follows:
GAIN = _V-----r-N-_e--_f--^C_----^O_1---^A--_–--^R--3---^S-N----2--^E_----F---×--⁺-_I---N----1-1--_{E----6-----}-- × _1--1--6--
= _V-----r^--_e^-N-_f^---₍^{C---5-O--1--A-2--R---}_–^{-S---E-N----+}_F^----_I^1-_N^----_E^---₎^{- × 32}
Where: V_ref = 2.5 V.
The gain correspondence is given in Table 3. The gain is
linear with reference to the programming code (N_FINE = 0).
CONTROL REGISTER
COAST and HSYNC signals can be inverted by setting the
I²C-bus control bits V level and H level respectively. When
V level and H level are set to zero respectively, COAST
and HSYNC are active HIGH.
The bit ‘edge’ defines the rising or falling edge of CKREF
to synchronise the PLL. It will be on the rising edge if the
bit is at logic 0 and on the falling edge if the bit is at logic 1.
The bits Up and Do are used for the test, to force the
charge pump current. These bits have to be logic 0 during
normal use.
The bits Ip0, Ip1 and Ip2 control the charge pump current,
to increase the bandwidth of the PLL, as shown in Table 5.
1999 Feb 24
18