TDA8376 Datasheet, PDF (29/44 Pages) NXP Semiconductors – I2C-bus controlled PAL/NTSC TV processors

Philips Semiconductors
I²C-bus controlled PAL/NTSC TV processors
Objective specification
TDA8376; TDA8376A
12. To obtain a good performance for both weak signal and VCR playback the time constant of the first control loop is
switched depending on the input signal condition and the condition of the I²C-bus. Therefore the circuit contains a
noise detector and the time constant is switched to ‘slow’ when too much noise is present in the signal. In the ‘fast’
mode during the vertical retrace time the phase detector current is increased 50% so that phase errors due to
head-switching of the VCR are corrected as soon as possible. Switching between the two modes can be
automatically or overruled by the I²C-bus.
The circuit contains a video identification circuit which is independent of first loop. This identification circuit can be
used to close or open the first control loop when a video signal is present or not present on the input. This enables
a stable On Screen Display (OSD) when just noise is present at the input. The coupling of the video identification
circuit with the first loop can be defeated via the I²C-bus.
To prevent that the horizontal synchronization being disturbed by anti-copy guard signals like Macrovision the phase
detector is gated during the vertical retrace period so that pulses during scan have no effect on the output voltage.
The width of the gate pulse is approximately 22 µs, the phase position around the sync pulse is asymmetrical. During
weak signal conditions (noise detector active) the gating is active during the complete scan period and the width of
the gate pulse is reduced to 5.7 µs so that the effect of the noise is reduced to a minimum.
The output current of the phase detector in the various conditions are shown in Table 39.
13. The ICs have two protection inputs. The protection on pin 43 is intended to be used as ‘flash’ protection. When this
protection is activated the horizontal drive pulse is switched-off immediately and then switched on again via the slow
start procedure. The protection on pin 49 is intended for overvoltage (X-ray) protection. When this protection is
activated the horizontal drive can be switched-off (via the slow stop procedure). It is also possible to continue the
horizontal drive and to set the protection bit (XPR) in the output bytes of the I²C-bus. The choice between the two
modes of operation is made via the PRD bit.
14. During switch-on the horizontal output starts with the double frequency and with a duty factor of 75% (V_HOUT = high).
After approximately 50 ms the frequency is changed to the normal value. Because of the high frequency the peak
currents in the horizontal output transistor are limited. Also during switch-off the frequency is switched to the double
value and the RGB drive is set to maximum so that the EHT capacitor is discharged. After approximately 100 ms the
RGB drive is set to minimum and 50 ms later the horizontal drive is switched-off.
15. The timing pulses for the vertical ramp generator are obtained from the horizontal oscillator via a divider circuit. This
divider circuit has 3 modes of operation:
a) Search mode ‘large window’.
This mode is switched on when the circuit is not synchronized or when a non-standard signal (number of lines per
frame in the 50 Hz mode is between 311 and 314 and in the 60 Hz mode between 261 and 264). In the search mode
the divider can be triggered between line 244 and line 361 (approximately 45 to 64.5 Hz).
b) Standard mode ‘narrow window’.
This mode is switched on when more than 15 successive vertical sync pulses are detected in the narrow window.
When the circuit is in the standard mode and a vertical sync pulse is missing the retrace of the vertical ramp generator
is started at the end of the window. Consequently, the disturbance of the picture is very small. The circuit will switch
back to the search window when, for 6 successive vertical periods, no sync pulses are found within the window.
c) Standard TV-norm (divider ratio 525 (60 Hz) or 625 (50 Hz).
When the system is switched to the narrow window it is checked whether the incoming vertical sync pulses are in
accordance with the TV-norm. When 15 standard TV-norm pulses are counted the divider system is switched to the
standard divider ratio mode. In this mode the divider is always reset at the standard value even if the vertical sync
pulse is missing.
When 3 vertical sync pulses are missed the system switches back to the narrow window and when also in this
window no sync pulses are found (condition 3 missing pulses) the system switches over to the search window.
The vertical divider requires some waiting time during channel-switching of the tuner. When a fast reaction of the
divider is required during channel-switching the system can be forced to the search window by means of the NCIN bit
in subaddress 08.
1996 Jan 26
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