TDA8376 Datasheet, PDF (22/44 Pages) NXP Semiconductors – I2C-bus controlled PAL/NTSC TV processors

Philips Semiconductors
I²C-bus controlled PAL/NTSC TV processors
Objective specification
TDA8376; TDA8376A
SYMBOL
PARAMETER
CONDITIONS
FLYBACK PULSE INPUT (PIN 41)
V_HSW
switching voltage level for horizontal
blanking
V_ϕ2(SW)
V_41(max)
Z_i
switching level for phase-2 loop
maximum input voltage
input impedance
note 7
note 7
SANDCASTLE PULSE OUTPUT (PIN 39)
V₃₉
output voltage
during burst key
during blanking
t_W
pulse width
burst key pulse
vertical blanking (50 Hz)
vertical blanking (60 Hz)
V_clamp
clamping voltage level for vertical
guard detection
I_39(min)
minimum input current to activate
guard detection
I_39(max)
t_d
maximum allowable input current
delay of start of burst key to start of
sync
Vertical synchronization and geometry correction
VERTICAL OSCILLATOR; note 15
f_fr
free running frequency
f_lock
locking frequency range
divider value not locked
LR
locking range
VERTICAL RAMP GENERATOR (PIN 50)
V_50(p-p)
sawtooth voltage amplitude
(peak-to-peak value)
I_dis
I_charge
discharge current
charge current set by external
resistor
VS
vertical slope control range
∆I₅₀
charge current increase
V_50L
LOW level voltage of ramp
VERTICAL DRIVE OUTPUTS (PINS 47 AND 48)
I_diff(p-p)
differential output current
(peak-to-peak value)
I_CM
common mode output current
V_o
output voltage
VS = 1FH;
C = 100 nF; R = 39 kΩ
note 16
63 steps
f = 60 Hz
VA = 1FH
MIN. TYP. MAX. UNIT
−
0.4
−
V
−
4.0
−
V
−
8.0
−
V
−
10
−
MΩ
4.8
5.3
1.8
2.0
3.3
3.5
−
25
−
21
−
2.7
−
−
2.5
−
−
5.4
5.8
V
2.2
V
3.7
µs
−
lines
−
lines
−
V
0.5
mA
−
mA
−
µs
−
50/60 −
Hz
45
−
64.5 Hz
−
625/525 −
lines
488 −
722 lines/
frame
−
3.5
−
1
−
19
−20 −
−
20
−
2.07
−
V
−
mA
−
µA
+20 %
−
%
−
V
−
0.95
−
mA
−
400
−
µA
0
−
4.0
V
1996 Jan 26
22