TDA8376 Datasheet, PDF (15/44 Pages) NXP Semiconductors – I2C-bus controlled PAL/NTSC TV processors

Philips Semiconductors
I²C-bus controlled PAL/NTSC TV processors
Objective specification
TDA8376; TDA8376A
Table 12 Vertical divider mode
NCIN
0
1
VERTICAL DIVIDER MODE
normal operation
switched to search window
Table 13 Video identification mode
VID
VIDEO IDENTIFICATION MODE
0 ϕ₁ loop switched on and off
1 not active
Table 14 Long blanking mode
LBM
0
1
BLANKING MODE
adapted to standard (50 or 60 Hz)
fixed in accordance with 50 Hz standard
Table 15 EHT tracking mode
HCO
0
1
TRACKING MODE
EHT tracking only on vertical
EHT tracking on vertical and E-W
Table 16 Enable vertical guard (RGB blanking)
EVG
0
1
VERTICAL GUARD MODE
not active
active
Table 17 Service blanking
SBL
0 off
1 on
SERVICE BLANKING MODE
Table 18 Overvoltage input mode
PRD
0
1
OVERVOLTAGE MODE
detection mode
protection mode
Table 19 Vertical deflection mode (TDA8376 only)
EXP
0
0
1
1
CL VERTICAL DEFLECTION MODE
0 normal
1 compress
0 expand
1 expand and lift
Table 20 Condition Y/C input
CVS
0
1
Y-INPUT MODE
switched to Y/C mode
switched to CVBS mode
Table 21 PAL/NTSC matrix
MAT
0
1
MATRIX
adapted to standard
PAL
Table 22 Y-delay adjustment; note 1
YD0 to YD3
Y-DELAY
YD3
YD3 × 160 ns +
YD2
YD2 × 80 ns +
YD1
YD1 × 40 ns +
YD0
YD0 × 40 ns
Note
1. For an equal delay of the luminance and chrominance
signal the delay must be set at a value of 160 ns. This
is only valid for a CVBS signal without group
delay distortions.
Table 23 RGB blanking
RBL
0
1
not active
active
RGB BLANKING
Table 24 Noise coring (peaking)
COR
0 off
1 on
NOISE CORING
Table 25 Enable fast blanking RGB1
IE1
FAST BLANKING
0 not active
1 active
Table 26 Enable fast blanking RGB2
IE2
FAST BLANKING
0 not active
1 active
1996 Jan 26
15