TDA8376 Datasheet, PDF (20/44 Pages) NXP Semiconductors – I2C-bus controlled PAL/NTSC TV processors

Philips Semiconductors
I²C-bus controlled PAL/NTSC TV processors
Objective specification
TDA8376; TDA8376A
SYMBOL
PARAMETER
LUMINANCE INPUTS AND OUTPUTS (PINS 27 AND 28)
V_28(p-p)
output signal voltage amplitude
(peak-to-peak value)
V_TS
Z_o
V_27(p-p)
top sync voltage level
output impedance
input signal voltage amplitude
(peak-to-peak value)
I_clamp
clamping current during burst key
pulse
I_i
input current
Chrominance filters
CHROMINANCE TRAP CIRCUIT
f_trap
trap frequency
QF
trap quality factor
SR
colour subcarrier rejection
CHROMINANCE BAND-PASS CIRCUIT
f_c
QBP
centre frequency
band-pass quality factor
Delay line, peaking circuit and black stretcher
Y DELAY LINE
t_d
delay time
t_d1
tuning range delay time
B
bandwidth of internal delay line
PEAKING CONTROL; note 9
f_c(p)
peaking centre frequency
t_W
width of preshoot or overshoot
OS
overshoot
peaking control curve
G_W
wave gain
CORING STAGE
S
coring range
BLACK LEVEL STRETCHER (PIN 2); note 10
BLS_max
LSH
maximum black level shift
level shift
CONDITIONS
top sync to white
no clamping
during SECAM reception
note 8
note 2
8 steps
note 2
at 50% of pulse; note 2
positive
negative
16 steps
n--p--e-o--g-s---ai--t-ti--iv-v--e-e----h-h--a-a--l--lf-f--w-w----a-a--v-v--e-e----g-g--a-a---i-in-n--
100% of peak-white
50% of peak-white
15% of peak-white
MIN. TYP. MAX. UNIT
−
0.45
0.63 V
−
2.5
−
V
−
250
−
Ω
−
0.45
−
V
−
200
−
µA
−
−
0.5
µA
−
f_osc
−
−
4.2
−
−
2
−
20
−
−
−
f_osc
−
−
3
−
MHz
MHz
dB
MHz
−
480
−160 −
5
−
−
+160
−
ns
ns
MHz
−
3
−
MHz
−
160
−
ns
−
20
−
%
−
36
−
%
see Fig.5
−
1.8
−
−
15
15
21
−1
0
−1
−
6
8
−
IRE
27
IRE
+1
IRE
+3
IRE
10
IRE
1996 Jan 26
20