TDA8594_15 Datasheet, PDF (28/49 Pages) NXP Semiconductors – I2C-bus controlled 4  50 W power amplifier

NXP Semiconductors
TDA8594
I²C-bus controlled 4  50 W power amplifier
Table 17. Characteristics …continued
Refer to Figure 29 at V_P = V_P1 = V_P2 = 14.4 V; R_L = 4 ; f = 1 kHz; R_S = 0 ; normal mode; unless otherwise specified.
Tested at T_amb = 25 C; guaranteed for T_amb = 40 C to +105 C.
Symbol
Parameter
Conditions
Min Typ Max Unit
Mode select and second clip detection: pin STB
V_STB
voltage on pin STB
Standby mode selected
I²C-bus mode
-
-
1
V
legacy mode (I²C-bus off)
-
-
1
V
mute selected
legacy mode (I²C-bus off)
2.5 -
4.5 V
Operating mode selected
I²C-bus mode
legacy mode (I²C-bus off)
low voltage on pin STB when
pulled down during clipping
2.5 -
6.5 -
[2]
V_P
V
V_P
V
I_STB = 150 A
5.6 -
6.1 V
I_STB = 500 A
6.1 -
7.2 V
I_STB
current on pin STB
V_STB = 0 V to 8.5 V
clip detection not active;
I²C-bus mode
-
4
30
A
legacy mode
-
10
70
A
Start-up, shut-down and mute timing
t_wake
wake-up time
time after wake-up via STB pin
-
300 500 s
before first I²C-bus transmission
is recognized; see Figure 3
I_LO(SVR)
output leakage current on pin
SVR
-
-
10
A
t_{d(mute_off)}
mute off delay time
10 % of output signal; I_LO = 0 A ^[3]
I²C-bus mode;
295 465 795 ms
with I_LO = 10 A  +15 ms;
no DC load (IB1[D1] = 0);
low pop disabled (IB2[D3] = 1);
see Figure 3
I²C-bus mode;
with I_LO = 10 A  +20 ms;
DC load active (IB1[D1] = 1);
low pop disabled (IB2[D3] = 1);
see Figure 4
500 640 940 ms
I²C-bus mode;
with I_LO = 10 A  +20 ms;
DC load active (IB1[D1] = 1);
low pop enabled (IB2[D3] = 0);
see Figure 5
640 830 1190 ms
legacy mode;
with I_LO = 10 A  +20 ms;
V_STB = 7 V; R_ADSEL = 0 ;
see Figure 6
430 650 1030 ms
TDA8594
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 11 June 2013
© NXP B.V. 2013. All rights reserved.
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