TDA8594_15 Datasheet, PDF (18/49 Pages) NXP Semiconductors – I2C-bus controlled 4  50 W power amplifier

NXP Semiconductors
TDA8594
I²C-bus controlled 4  50 W power amplifier
The interpretation of line driver and normal mode DC load bit settings for AC load
detection is shown in Table 6.
Table 6.
DBx[D4]
0
1
AC load detection
Meaning (when IB1[D2] = 1)
no AC load detected
AC load detected
When bit IB1[D2] = 1, the AC load detection is enabled. The AC load detection can only
be performed after the amplifier has completed its start-up cycle and will not conflict with
the DC load detection.
20
|Z_th(load)|
(Ω)
16
12
001aad177
(1)
8
(2)
4
0
0
1
2
3
4
5
V_oM (V)
(1) I_{th(o)det(load)AC} < 230 mA (no load detection level)
(2) I_{th(o)det(load)AC} > 460 mA (load detection level)
Fig 13. AC load impedance as a function of peak output voltage
7.17 I²C-bus diagnostic readout
The diagnostic information of the amplifier can be read via the I²C-bus. The I²C-bus bits
are set on a failure and will be reset with the I²C-bus read command. Even when the
failure is removed, the microprocessor will know what was wrong by reading the I²C-bus.
The consequence of this procedure is that old information is read during the I²C-bus
readout. Most actual information will be gathered after two successive read commands.
The DIAG pin will give actual diagnostic information (when selected). When a failure is
removed, the DIAG pin will be released instantly, independently of the I²C-bus latches.
TDA8594
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 11 June 2013
© NXP B.V. 2013. All rights reserved.
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