MN5572 Datasheet, PDF(4/28 Page) Panasonic Semiconductor

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MN5572 Datasheet, PDF (4/28 Pages) Panasonic Semiconductor – Gray Scale Font Engine

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MN5572

I Pin Descriptions

1. Local 32 mode pin descriptions

Pin Name

I/O

Description

ICLOCK

I Internal operating clock input

HOSTCLK

I External interface clock input

NRST

I Hardware reset (active low)

ADRS[3 : 0]

I Address input from host

NCS

I Chip select from host (active low)

NWE

I Write enable from host (active low)

NRE

I Read enable from host (active low)

DATA[31 : 16]

I/O Data I/O to/from host (upper 16 bits)

DATA[15 : 0]

I/O Data I/O to/from host (lower 16 bits)

WAIT

O Wait output to host

IRQ

O Interrupt request output to host

IFCFG

I Interface mode setting (connect low)

BUSSEL

I Data bus width setting (connect high)

CLKSEL[2 : 0]

Internal/external clock setting

PLNRESET

I Internal PLL reset (active low)

P1NPWD

I Low power mode control for internal frequency multiplier PLL (active low)

P1SEL[2 : 1]

I Frequency selector for internal frequency multiplier PLL

P2NPWD

I Low power mode control for external phase compensation PLL (active low)

OCLOCK

O Unused

NSERR

I Unused

NPERR

I Unused

PAR

I Unused

NSTOP

I Unused

NDEVSEL

I Unused

MINTEST