MN5572 Datasheet, PDF(11/28 Page) Panasonic Semiconductor

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MN5572 Datasheet, PDF (11/28 Pages) Panasonic Semiconductor – Gray Scale Font Engine

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MN5572

I Functional Description (continued)

2. Memory register functions (continued)

2.4 STATUS register (continued)

bit 15 14 13 12 11 10

PMS

RMS REC

RVS

543210

0 MIS 0 CES CCS

PMS:

RMS:

REC:

RVS:

MIS:

CES:

CCS:

Indicates the status of the POINT FIFO. After a reset, the status will be FIFO empty.

11: FIFO full (Write not allowed)

01: FIFO ready (Write allowed)

00: FIFO empty (Write wait state)

Indicates the status of the RASTER FIFO. During a reset, the status will be FIFO empty.

11: FIFO full (Read wait state)

01: FIFO ready (Read allowed)

00: FIFO empty (Read not allowed)

Indicates whether or not the end of a single frame occurs within the 64 double-word values to be read out.

1: The readout of a single frame will be completed by reading out the data indicated by RVS.

0: The end of a frame does not exist in the data indicated by RVS.

Indicates the amount of data that can be read out from the RASTER FIFO.

Up to 64 double-word values (0x00 to 0x3F)

Indicates the IC internal initialization state.

An initialization operation is executed automatically after a reset.

1: Initializing (Initialization in progress)

0: Initialized (Initialization complete)

Indicates the IC internal execution state.

0: Run mode

Indicates the sleep state.

1: Sleep mode

2.5 MASK register

Readable/writable register that sets the interrupt generation conditions for the MN5572.

This is a 16-bit register. Only the low-order 16 bits of the data bus are used.

bit 15

PM ï£§ ï£§ ï£§ ï£§ ï£§ ï£§

RM ï£§ ï£§ ï£§ ï£§ ï£§ ï£§ TM

PM: Setting this bit enables the MN5572 to generate interrupt requests (IRQ) according to the PMS state.

1: Interrupts generated on FIFO empty.

0: Interrupt disabled. (default)

RM: Setting these bits enables the MN5572 to generate interrupt requests (IRQ) according to the RMS state.

11: Interrupts generated on FIFO full. (default)

01: Interrupts generated on FIFO ready.

00: Interrupt disabled.

TM: Setting this bit enables the MN5572 to generate interrupt requests (IRQ) according to the state of the MIS flag.

1: An interrupt is generated after initialization completes. (default)

0: Interrupt disabled.

SDF00008BEM

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