MN5572 Datasheet, PDF (16/28 Pages) Panasonic Semiconductor – Gray Scale Font Engine

MN5572
I Operation
1. Pin settings
This section describes the pin setting conditions that control the operating state of the MN5572.
1. 1. Clock settings
The interface clock and the internal operating clock are set using the clock setting pins, CLKSEL[2:0].
The application must provide the same external clock signal to the HOSTCLK (PCICLK) and ICLOCK pins.
CLKSEL2 CLKSEL1 CLKSEL0
Interface block clock
Internal operating clock
0
0
0
HOSTCLK (PCICLK) phase compensation applied Multiplier of ICLOCK
0
0
1
HOSTCLK (PCICLK) phase compensation applied
ICLOCK
0
1
0
HOSTCLK (PCICLK) phase compensation applied ICLOCK duty compensation applied.
0
1
1
HOSTCLK (PCICLK) phase compensation applied
ICLOCK
1. 2. Phase compensation circuit settings
The interface clock phase compensation circuit is set from external pins. These settings are required when the
PCI interface is used.
Pin Name
Setting
PLNRESET This pin should be held low (reset) when power
is applied, and the held high at other times.
HOSTCLK(PCICLK)
Input frequency: 13 MHz to 33 MHz
P2NPWD
Connect high.
Notes
When the circuit is not used, this pin
may be held low to save power.
1. 3. Frequency multiplier circuit settings
The internal operating clock frequency multiplier circuit can be set by external pins.
• When the clock setting pins CLKSEL[1:0] are 00 (Multiplied clock setting)
Pin Name
PLNRESET
ICLOCK
P1NPWD
P1SEL[2 : 1]
Setting
This pin should be held low (reset) when power
is applied, and the held high at other times.
Input frequency
Connect high.
Multiplier setting
Notes
When the circuit is not used, this pin
may be held low to save power.
P1SEL2
0
0
1
P1SEL1 Multiplier
0
forbidden
1
2
0
4
ICLOCK frequency

26 MHz to 33 MHz
13 MHz to 16.5 MHz
Internal operating frequency

52 MHz to 66 MHz
52 MHz to 66 MHz
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