MN5572 Datasheet, PDF (26/28 Pages) Panasonic Semiconductor – Gray Scale Font Engine

MN5572
I Electrical Characteristics (continued)
4. PLL Characteristics (continued)
<PLL Reset Timing: ICLOCK>
You should insert a delay of at least 50 ns after the rise of either P1VDD or P1NPWD, whichever occurs later,
and then bring PLNRESET up to the high level.
Also, if P1VDD is high, you should raise PLNRESET when P1NPWD is set low.
(1)
P1VDD
P1NPWD
PLNRESET
50 nsec
(2)
P1NPWD
P1VDD
PLNRESET
50 nsec
<PLL Reset Timing: PCICLK>
You should insert a delay of at least 50 ns after the rise of either P2VDD or P2NPWD, whichever occurs later,
and then bring PLNRESET up to the high level.
Also, if P2VDD is high, you should raise PLNRESET when P2NPWD is set low.
(1)
P2VDD
P2NPWD
PLNRESET
50 nsec
(2)
P2NPWD
P2VDD
PLNRESET
50 nsec
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