PYTHON25K Datasheet, PDF (60/87 Pages) ON Semiconductor – PYTHON 25K/16K/12K/10K Global Shutter CMOS Image Sensors

NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
Table 30. REGISTER MAP
Category
Block
Offset
Address
Offset
Address
Bit
Field
[6]
Register Name
nzrot_xsm_delay_en-
able
[7]
subsampling
[8]
binning
[10]
[13:11]
reserved
monitor_select
[14]
reserved
[15]
sequence
1
193
reserved
[7:0]
reserved
[15:8] reserved
2
194
integration_control
[0]
reserved
[1]
reserved
[2]
fr_mode
[3]
reserved
[4]
int_priority
[5]
halt_mode
[6]
fss_enable
[7]
fse_enable
[8]
reverse_y
[9]
reserved
Default
(Hex)
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0000
0x00
0x00
0x00E4
0x0
0x0
0x1
0x0
0x0
0x1
0x1
0x1
0x0
0x0
Default
0
0
0
0
0
0
0
0
0
0
228
0
0
1
0
0
1
1
1
0
0
Description
Insert delay between
end of ROT and start of
readout in normal ROT
readout mode if ‘1’.
ROT delay is defined by
register xsm_delay
Subsampling mode
selection
‘0’: no subsampling,
‘1’: subsampling
Binning mode selection
‘0’: no binning,
‘1’: binning
Reserved
Control of the monitor
pins
Reserved
Enable a sequenced
readout with different
parameters for even and
odd frames.
Reserved
Reserved
Reserved
Integration Control
Reserved
Reserved
Representation of
fr_length.
‘0’: reset length
‘1’: frame length
Reserved
Integration Priority
‘0’: Frame readout has
priority over integration
‘1’: Integration End has
priority over frame read-
out
The current frame will be
completed when the
sequencer is disabled
and halt_mode = ‘1’.
When ‘0’, the sensor
stops immediately when
disabled, without fin-
ishing the current frame.
Generation of Frame
Sequence Start Sync
code (FSS)
‘0’: No generation of
FSS
‘1’: Generation of FSS
Generation of Frame
Sequence End Sync
code (FSE)
‘0’: No generation of
FSE
‘1’: Generation of FSE
Reverse readout
‘0’: bottom to top readout
‘1’: top to bottom readout
Reserved
Type
RW
RW
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