PYTHON25K Datasheet, PDF (11/87 Pages) ON Semiconductor – PYTHON 25K/16K/12K/10K Global Shutter CMOS Image Sensors

NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
OVERVIEW
Figure 9 gives an overview of the major functional blocks of the PYTHON sensor.
Image Core Bias
Image Core
Pixel Array
Control & Registers
LVDS Clock
Receiver
Column Structure
64 analog channels
Analog Front End (AFE)
64 x 10 bit
digital channels
Data Formatting
32 x 10 bit
digital channels
Serializers & LVDS Interface
Biasing &
Bandgap
External
Resistor
SPI
Reset
Interface
32, 16, 8, 4 Multiplexed LVDS Output Channels
1 LVDS Channel
1 LVDS Clock Channel
Figure 9. Block Diagram
Image Core
The image core consists of:
• Pixel array
• Address decoders and row drivers
• Pixel biasing
The PYTHON 25MP pixel array contains 5120 (H) x
5120 (V) readable pixels with a pixel pitch of 4.5 mm.
The PYTHON 16MP/12MP/10MP image arrays contain
4224 (H) x 4112 (V) / 4224 (H) x 3088 (V) / 3968 (H) x
2912 (V) readable pixels, inclusive of 8 pixel rows and 64
pixel columns at every side to allow for reprocessing or color
reconstruction. The sensor uses in-pixel CDS architecture,
which makes it possible to achieve a low noise read out of
the pixel array in both global shutter shutter mode with CDS.
The function of the row drivers is to access the image array
to reset or read the pixel data. The row drivers are controlled
by the on-chip sequencer and can access the pixel array.
The pixel biasing block guarantees that the data on a pixel
is transferred properly to the column multiplexer when the
row drivers select a pixel line for readout.
LVDS Clock Receiver
The LVDS clock receiver receives an LVDS clock signal
and distributes the required clocks to the sensor.
Typical input clock frequency is 360 MHz. The clock
input needs to be terminated with a 100 W resistor.
Column Multiplexer
The 5120 pixels of one image row are stored in 5120
column sample-and-hold (S/H) stages. These stages store
both the reset and integrated signal levels.
The data stored in the column S/H stages is read out
through 64 parallel differential outputs operating at a
frequency of 36 MHz.
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