PYTHON25K Datasheet, PDF (36/87 Pages) ON Semiconductor – PYTHON 25K/16K/12K/10K Global Shutter CMOS Image Sensors

NOIP1SN025KA, NOIP1SN016KA, NOIP1SN012KA, NOIP1SN010KA
DATA OUTPUT FORMAT
LVDS Output Channels
The image data output occurs through 32 LVDS data
channels, operating at 720 Mbps. A synchronization LVDS
channel and an LVDS output clock signal synchronizes the
data.
The 32 data channels are used to output the image data
only. The sync channel transmits information about data sent
over these data channels (includes codes indicating black
pixels, normal pixels, and CRC).
To perform word synchronization on the output data
stream, a predefined training pattern is sent after startup of
the sensor and during idle times (during FOT, ROT, and in
between frames and lines). This data is used to perform word
alignment on the receiving side.
The words on data and sync channels have a 10-bit length.
The words are serialized most significant bit first. The
output data rate is 720 Mbps.
Serial Link Interface Operation
This sensor’s serial link interface is based on a
mesochronous clocking system. This means that all data and
control links operate at the same frequency, but their phase
may be different due to skew. The host provides an LVDS
clock as input to the sensor. To compensate for possible large
on-chip delays, the sensor retransmits this clock with the
same delay as that seen by the data (32 data channels) and
control path (one sync channel). The receiver end (generally
an FPGA-based system) performs per-interface skew
compensation.
The data on high-speed serial links can drift due to various
reasons such as skew, jitter, PCB trace delays, process,
voltage, and temperature variations. The receiver performs
per-LVDS interface skew compensation using bit and word
alignment techniques.
To support per-interface skew compensation, the sensor
provides a training mode that allows the system to perform
bit and word alignment on all interfaces.
During idle moments (when the sensor is not capturing
images or during frame and line overhead), the image sensor
transmits training patterns. These patterns are configurable
by means of a register upload and should be chosen such that
these can easily be detected by reducing the risk of
mimicking in the regular data stream.
Bit Alignment
Bit alignment procedures position the sampling edge of
the clock at the center of the data eye window by adding
delay to the data path (using delay taps).
Word Alignment
Word alignment procedures ensure that the reconstructed
parallel data bits are in correct order at the output of the
deserializer. Word alignment is done by looking for well
known training patterns.
All major FPGA vendors provide bit and word alignment
methods for their FPGAs. Refer to the FPGA vendor’s
application for more information on the use of these
functionalities.
When the host succeeds in a lock for bit and word
alignment procedures, the system enables the sensor for
image acquisition. Specific frame alignment patterns are
transmitted for image frame synchronization purposes.
Frame Format
The frame format is explained by example of the readout
of two (overlapping) windows, as shown in Figure 30 (a).
The readout of a frame occurs on a line-by-line basis. In
this representation, the read pointer goes from left to right,
bottom to top.
Figure 30 indicates that, after the FOT is complete, a
number of lines which only include information of ‘ROI 0’
are sent out, starting at position y0_start. When the line at
position y1_start is reached, a number of lines containing
data of ‘ROI 0’ and ‘ROI 1’ are sent out, until the line
position of y0_end is reached. From there on, only data of
‘ROI 1’ appears on the data output channels until line
position y1_end is reached.
NOTE: Only frame start and frame end sync words are
indicated in (b). CRC codes are also omitted
from Figure 30.
During readout of image data over the data channels, the
sync channel sends out frame synchronization codes, which
provide information related to the image data being sent
over the 32 data output channels.
Each line of a window starts with a line start (LS)
indication and ends with a line end (LE) indication. The line
start of the first line is replaced by a frame start; the line end
of the last line is replaced with a frame end indication. Each
such frame synchronization code is followed by a window
ID (range 0 to 31).
The data channels contain valid pixel data during
FS/FE/LS/LE and window ID synchronization codes.
NOTE: For overlapping windows, the line
synchronization codes of the overlapping
windows with lower IDs are not sent out. As
shown in the illustration, no LE is transmitted
for the overlapping part of window 0.
Black lines are read out at the start of a frame. These lines
are enclosed by LS and LE indications (no frame start/end).
The window ID for the black lines must be ignored.
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