LC89058W-E Datasheet, PDF (40/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

12.1.6 I/O timing
LC89058W-E
CE
CL
DI
B0 B1 B2 B3 A0 A1 A2 A3
CAL
CAU DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI1 DI2 ^{⋅⋅⋅ ⋅⋅â‹} DI15
DO
Hi-Z
Figure 12.1 Input Timing Chart (Normal L clock)
CE
CL
DI
B0 B1 B2 B3 A0 A1 A2
A3
CAL CAU DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 DI11 DI12 ^{⋅⋅⋅ ⋅⋅â‹} DI15
DO
Hi-Z
Figure 12.2 Input Timing Chart (Normal H clock)
(CL need not be lowered before CE is raised.)
CE
CL
DI
B0 B1 B2 B3 A0 A1 A2 A3
DO
Hi-Z
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8 ^{⋅⋅⋅ ⋅⋅⋅ ⋅⋅⋅ ⋅⋅⋅ ⋅⋅⋅ ⋅⋅â‹} DOn
Figure 12.3 Output Timing Chart (Normal L clock)
CE
CL
DI
B0 B1 B2 B3 A0 A1 A2 A3
DO
Hi-Z
DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 ^{⋅⋅⋅ ⋅⋅⋅ ⋅⋅⋅ ⋅⋅⋅ ⋅⋅⋅ ⋅⋅⋅ ⋅⋅â‹} DOn
Figure 12.4 Output Timing Chart (Normal H clock)
(CL is lowered before CE is raised, and DO0 need be read with port)
No.A1056-40/64