LC89058W-E Datasheet, PDF (25/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
10.1.9 Output of clock switch transition signal (CKST)
• CKST outputs pulse when the output clock changes by PLL lock/unlock.
• The polarity of the CKST pulse output can be reversed with CKSTP. Subsequently, CKSTP is assumed to be 0.
• In the lock-in stage, the CKST falls at the word clock generated from the XIN clock after PLL is locked following
detection of input data, and rises at the same timing as RERR after a designated period.
• In the unlock stage, the CKST falls at the same timing as RERR, PLL lock detection signal, and rises after word
clocks generated from the XIN clock are counted for a designated period.
• Change of the PLL lock status and timing of the clock change can be seen by detecting the rising and falling edges
and pulses of CKST.
• The clock is switched after the PLL lock condition is tested and identified. The timing of this clock switching is
determined by setting the PTOXW [1:0]. The initial value is such that the clock is switched in 2.7ms after the falling
edge of CKST. The value, however, assumes that the oscillation amplifier is set to permanent operation mode. If the
oscillation amplifier is set to be stopped after PLL locking, the startup time before the oscillation amplifier stabilizes
after PLL unlocking, is added.
• A free-running clock is output from the clock output pin immediately after PLL unlocking.
RX0 to RX6
Digital data
PLL status
UNLOCK
LOCK
XIN clock
PLL clock
CKST (CKSTP=0)
After PLL lock 3ms to 144ms
RERR
RMCK
2.7ms
XIN clock
PLL clock
(a): Lock-in stage
RX0 to RX6
Digital data
PLL status
LOCK
UNLOCK
XIN clock
PLL clock
CKST (CKSTP=0)
Same timing as RERR
5.3ms
RERR
RMCK
2.7ms**
PLL clock
**: When set to PTOXW[1:0]=00 (max.)
XIN clock
(b): Unlock stage
Figure 10.5 Clock Switch Timing
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