LC89058W-E Datasheet, PDF (22/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
10.1.6 PLL clock output
• The PLL clock output is controlled by the PLLACC, PLLDV1, PLLDV2, or PRSEL[1:0].
• PLLACC can be used to generate a PLL lock frequency for each S/PDIF input sampling frequency band.
S/PDIF Input
512fs
Lock detection
Lock
Unlock
Fs calculation
PLL output
Free-run
*: When the data is judged to exceed the value of
FSLIM [1:0] which limits the reception frequency of
the input S/PDIF, processing similar to PLL
unlocking is carried out and the processing does not
proceed to the subsequent step. The clock source is
automatically switched to the XIN source.
“PLLACC”
1
*
0
Fs=
No
32k, 44.1k, 48k
Yes
0
“PLLDV0”
1
PLL output
256fs
PLL output
512fs
PLL fixation output
“PRSEL=00”: 256fs
“PRSEL=01”: 512fs
“PRSEL=10”: 128fs
Fs=
No
64k, 88.2k, 96k
Yes
0
“PLLDV1”
1
PLL output
512fs
PLL output
256fs
Fs=
No
128k, 176.4k, 192k
Yes
PLL output
128fs
PLL output
256fs
Figure 10.3 PLL Clock Output Control
Table 10.2: PLL Clock Output Frequencies (Bold settings are recommended values.)
PLL Output
S/PDIF
fs
PLLACC=0 (Fixed multiple outputs of input fs)
PRSEL=00
(256fs)
PRSEL=01
(512fs)
PRSEL=10
(128fs)
PLLACC=1 (Fixed multiple outputs for each input fs band)
PLLDV0=0
PLLDV1=0
PLLDV0=1
PLLDV1=0
PLLDV0=0
PLLDV1=1
PLLDV0=1
PLLDV1=1
32kHz
8.19MHz
16.38MHz
4.09MHz
16.38MHz
8.19MHz
16.38MHz
8.19MHz
44.1kHz
11.28MHz
22.57MHz
5.64MHz
22.57MHz
11.28MHz
22.57MHz
11.28MHz
48kHz
12.28MHz
24.57MHz
6.14MHz
24.57MHz
12.28MHz
24.57MHz
12.28MHz
64kHz
16.38MHz
32.76MHz
8.19MHz
16.38MHz
16.38MHz
32.76MHz
32.76MHz
88.2kHz
22.57MHz
45.15MHz
11.28MHz
22.57MHz
22.57MHz
45.15MHz
45.15MHz
96kHz
24.57MHz
49.15MHz
12.28MHz
24.57MHz
24.57MHz
49.15MHz
49.15MHz
128kHz
32.76MHz
65.53MHz
16.38MHz
16.38MHz
16.38MHz
16.38MHz
16.38MHz
176.4kHz
45.15MHz
90.31MHz
22.57MHz
22.57MHz
22.57MHz
22.57MHz
22.57MHz
192kHz
49.15MHz
98.30MHz
24.57MHz
24.57MHz
24.57MHz
24.57MHz
24.57MHz
• If 128kHz, 176.4kHz or 192kHz input is received when the PLLACC is set to 0 and the PRSEL [1:0] to 01, the DC
characteristics of output directly sent to the RMCK pin cannot be guaranteed. In such a case, set the frequency to one
half or quarter of the PLL clock frequency (PRSEL [1:0]=00 or 10).
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