LC89058W-E Datasheet, PDF (24/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
10.1.8 Output clocks block diagram (RMCK, RBCK, RLRCK, SBCK, SLRCK, XMCK)
• The relationships between the output clock and switch function are shown below.
• PLL in the figure indicates the PLL source and XIN the XIN source.
• The contents in the quotation marks “∗∗∗” by the switch function blocks correspond to the write command names.
• The broken lines connecting the switches indicate coordinated switching.
• Lock/Unlock is switched automatically by PLL locking/unlocking.
Master
Clock
Generator
PLL Source
512fs
X’tal Source
12.288MHz
24.576MHz
512fs
“PLLDV0”
“PLLDV1”
1/1
1/2
1/4
Input fs
Auto
“PRSEL[1:0]”
512fs
256fs
128fs
Mute
“XINSEL”
12.288MHz
24.576MHz
Lock / Unlock
“OCKSEL”
“PLLACC”
PLL
“EXTSEL”
“XRSEL[1:0]”
1/1
1/2
1/4
Mute
XIN
GPIO0
“XMSEL[1:0]”
1/1
1/2
Mute
64fs
PLL
“RMCKP”
“EMCKP”
RMCK
XMCK
“XRBCK[1:0]”
12.288MH
6.144MHz
3.072MHz
Mute
XIN
GPIO1
fs
PLL
RBCK
“PSBCK[1:0]”
128fs
64fs
32fs
16fs
“PSLRCK[1:0]”
2fs
fs
fs/2
fs/4
“XRLRCK[1:0]”
192kHz
96kHz
48kHz
Mute
XIN
GPIO2
“SBCKP”
PLL
“XSBCK[1:0]”
12.288MH
6.144MHz
3.072MHz
Mute
XIN
“SLRCKP”
PLL
“XSLRCK[1:0]”
192kHz
96kHz
48kHz
Mute
XIN
RLRCK
Master / Slave
SBCK
SLRCK
Figure 10.4 Clock Output Block Diagram
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