LC89058W-E Datasheet, PDF (21/64 Pages) Sanyo Semicon Device – Digital Audio Interface Receiver

LC89058W-E
10.1.5 Master clock block diagram (XIN, XOUT, RMCK, XMCK)
• The relationships between the two types of PLL and XIN source master clocks, switching, and the frequency division
function are described below.
• The contents in the quotation marks “*** “ by the switch and function blocks correspond to the write command names.
• Lock/Unlock is automatically switched by PLL locking/unlocking.
“PLLOPR”
S/PDIF
PLL
512fs
XOUT
XIN
“AMPOPR[1:0]”
GPIO0
“PLLDV1”
“PLLDV2”
Auto 1/N
(N=1,2,4)
Lock/Unlock
“PLLACC”
1/N
(N=1,2,4)
“PRSEL[1:0]”
“XINSEL”
12.288M
24.567M
“XRSEL[1:0]”
1/N
(N=1,2,4)
“OCKSEL”
“RMCKP”
“EMCKP”
“XMSEL[1:0]”
1/N
(N=1, 2)
RMCK
“EXTSEL”
XMCK
Figure 10.2 Master Clock Block Diagram
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